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Searched refs:FalseReg (Results 1 – 21 of 21) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVVectorPeephole.cpp448 Register FalseReg = MI.getOperand(2).getReg(); in convertSameMaskVMergeToVMv() local
449 if (TruePassthruReg != FalseReg) { in convertSameMaskVMergeToVMv()
722 Register FalseReg = MI.getOperand(2).getReg(); in foldVMergeToMask() local
744 if (PassthruReg && !isKnownSameDefs(PassthruReg, FalseReg)) in foldVMergeToMask()
751 !isKnownSameDefs(TruePassthru, FalseReg)) in foldVMergeToMask()
807 True.getOperand(True.getNumExplicitDefs()).setReg(FalseReg); in foldVMergeToMask()
H A DRISCVInstrInfo.cpp1770 MachineOperand FalseReg = MI.getOperand(Invert ? 5 : 4); in optimizeSelect() local
1772 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
1794 NewMI.add(FalseReg); in optimizeSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86CmovConversion.cpp729 Register FalseReg = in convertCmovInstsToBranches() local
733 auto FRIt = FalseBBRegRewriteTable.find(FalseReg); in convertCmovInstsToBranches()
736 FalseReg = FRIt->second; in convertCmovInstsToBranches()
738 FalseBBRegRewriteTable[MI.getOperand(0).getReg()] = FalseReg; in convertCmovInstsToBranches()
H A DX86InstrInfo.h466 Register FalseReg) const override;
H A DX86InstrInfo.cpp4159 Register FalseReg, int &CondCycles, in canInsertSelect() argument
4173 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
4197 Register FalseReg) const { in insertSelect()
4206 .addReg(FalseReg) in insertSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp506 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2); in optimizeSelect() local
508 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
532 FalseReg.setImplicit(); in optimizeSelect()
533 NewMI.add(FalseReg); in optimizeSelect()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelperCasts.cpp213 Register FalseReg = Select->getFalseReg(); in matchCastOfSelect() local
225 auto False = B.buildInstr(Cast->getOpcode(), {DstTy}, {FalseReg}); in matchCastOfSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1521 Register FalseReg, int &CondCycles, in canInsertSelect() argument
1542 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
1568 Register FalseReg) const { in insertSelect()
1575 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in insertSelect()
1627 Register FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect()
1628 SecondReg = SwapOps ? TrueReg : FalseReg; in insertSelect()
3285 unsigned TrueReg, unsigned FalseReg, in selectReg() argument
3292 return Imm1 < Imm2 ? TrueReg : FalseReg; in selectReg()
3294 return Imm1 > Imm2 ? TrueReg : FalseReg; in selectReg()
3296 return Imm1 == Imm2 ? TrueReg : FalseReg; in selectReg()
[all …]
H A DPPCInstrInfo.h563 Register FalseReg) const override;
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp931 Register FalseReg = getRegForValue(Select->getFalseValue()); in selectSelect() local
932 if (FalseReg == 0) in selectSelect()
936 std::swap(TrueReg, FalseReg); in selectSelect()
979 .addReg(FalseReg) in selectSelect()
H A DWebAssemblyISelLowering.cpp550 unsigned Tmp0, Tmp1, CmpReg, EqzReg, FalseReg, TrueReg; in LowerFPToInt() local
555 FalseReg = MRI.createVirtualRegister(MRI.getRegClass(OutReg)); in LowerFPToInt()
588 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg).addReg(InReg); in LowerFPToInt()
592 .addReg(FalseReg) in LowerFPToInt()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.h260 Register FalseReg) const override;
H A DSystemZInstrInfo.cpp601 Register FalseReg, int &CondCycles, in canInsertSelect() argument
613 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
637 Register FalseReg) const { in insertSelect()
657 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg); in insertSelect()
659 FalseReg = FReg; in insertSelect()
670 .addReg(FalseReg).addReg(TrueReg) in insertSelect()
H A DSystemZISelLowering.cpp9581 Register FalseReg = MI->getOperand(2).getReg(); in createPHIsForSelects() local
9587 std::swap(TrueReg, FalseReg); in createPHIsForSelects()
9592 if (auto It = RegRewriteTable.find(FalseReg); It != RegRewriteTable.end()) in createPHIsForSelects()
9593 FalseReg = It->second.second; in createPHIsForSelects()
9598 .addReg(FalseReg).addMBB(FalseMBB); in createPHIsForSelects()
9601 RegRewriteTable[DestReg] = std::make_pair(TrueReg, FalseReg); in createPHIsForSelects()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp790 auto FalseReg = MIB.getReg(3); in selectSelect() local
792 validOpRegPair(MRI, TrueReg, FalseReg, 32, ARM::GPRRegBankID) && in selectSelect()
797 .addUse(FalseReg) in selectSelect()
H A DARMBaseInstrInfo.cpp2198 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1); in optimizeSelect() local
2201 const TargetRegisterClass *FalseClass = MRI.getRegClass(FalseReg.getReg()); in optimizeSelect()
2234 FalseReg.setImplicit(); in optimizeSelect()
2235 NewMI.add(FalseReg); in optimizeSelect()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.h377 Register TrueReg, Register FalseReg, int &CondCycles,
383 Register TrueReg, Register FalseReg) const override;
388 Register TrueReg, Register FalseReg) const;
H A DSIInstrInfo.cpp1193 Register FalseReg) const { in insertVectorSelect()
1205 .addReg(FalseReg) in insertVectorSelect()
1220 .addReg(FalseReg) in insertVectorSelect()
1234 .addReg(FalseReg) in insertVectorSelect()
1248 .addReg(FalseReg) in insertVectorSelect()
1264 .addReg(FalseReg) in insertVectorSelect()
1280 .addReg(FalseReg) in insertVectorSelect()
1298 .addReg(FalseReg) in insertVectorSelect()
3285 Register FalseReg, int &CondCycles, in canInsertSelect() argument
3292 if (MRI.getRegClass(FalseReg) != RC) in canInsertSelect()
[all …]
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetInstrInfo.h959 Register TrueReg, Register FalseReg, in canInsertSelect() argument
983 Register TrueReg, Register FalseReg) const { in insertSelect() argument
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.h411 Register FalseReg) const override;
H A DAArch64InstrInfo.cpp765 Register FalseReg, int &CondCycles, in canInsertSelect() argument
771 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)); in canInsertSelect()
793 else if (canFoldIntoCSel(MRI, FalseReg)) in canInsertSelect()
815 Register TrueReg, Register FalseReg) const { in insertSelect()
965 TrueReg = FalseReg; in insertSelect()
967 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg); in insertSelect()
971 FalseReg = NewVReg; in insertSelect()
980 MRI.constrainRegClass(FalseReg, RC); in insertSelect()
985 .addReg(FalseReg) in insertSelect()