Searched refs:DstOpcode (Results 1 – 2 of 2) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86DomainReassignment.cpp | 125 unsigned DstOpcode; member in __anond9661d290111::InstrReplacer
127 InstrReplacer(unsigned SrcOpcode, unsigned DstOpcode) in InstrReplacer() argument
128 : InstrConverterBase(SrcOpcode), DstOpcode(DstOpcode) {} in InstrReplacer()
138 !TII->get(DstOpcode).hasImplicitDefOfPhysReg(MO.getReg())) in isLegal()
147 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), TII->get(DstOpcode)); in convertInstr()
166 unsigned DstOpcode; member in __anond9661d290111::InstrReplacerDstCOPY
168 InstrReplacerDstCOPY(unsigned SrcOpcode, unsigned DstOpcode) in InstrReplacerDstCOPY() argument
169 : InstrConverterBase(SrcOpcode), DstOpcode(DstOpcode) {} in InstrReplacerDstCOPY()
178 TII->getRegClass(TII->get(DstOpcode), 0, MRI->getTargetRegisterInfo(), in convertInstr()
180 MachineInstrBuilder Bld = BuildMI(*MBB, MI, DL, TII->get(DstOpcode), Reg); in convertInstr()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMLatencyMutations.cpp | 535 unsigned DstOpcode = DstMI->getOpcode(); in makeBundleAssumptions() local
537 if (DstOpcode == ARM::BUNDLE && TII->isPredicated(*DstMI)) { in makeBundleAssumptions()
635 unsigned DstOpcode = DstMI->getOpcode(); in modifyBypasses() local
642 if (isNSWload && (II->isMultiply(DstOpcode) || II->isDivide(DstOpcode))) in modifyBypasses()
648 if (isNSWload && II->hasBRegAddr(DstOpcode) && in modifyBypasses()
655 unsigned OpMask = II->getAddressOpMask(DstOpcode) >> 1; in modifyBypasses()
673 if (II->isInlineShiftALU(DstOpcode) && DstMI->getOperand(3).getImm() && in modifyBypasses()
692 if (II->isInlineShiftALU(DstOpcode)) in modifyBypasses()
694 else if (II->isShift(DstOpcode)) in modifyBypasses()
885 unsigned DstOpcode = DstMI->getOpcode(); in modifyBypasses() local
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