Searched refs:DstInst (Results 1 – 5 of 5) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 444 MachineInstr *DstInst = Dst->getInstr(); in adjustSchedDependency() local
450 if (QII->canExecuteInBundle(*SrcInst, *DstInst) && in adjustSchedDependency()
458 if (DstInst->isCopy()) in adjustSchedDependency()
466 if ((DstInst->isRegSequence() || DstInst->isCopy())) { in adjustSchedDependency()
467 Register DReg = DstInst->getOperand(0).getReg(); in adjustSchedDependency()
503 if (EnableDotCurSched && QII->isToBeScheduledASAP(*SrcInst, *DstInst) && in adjustSchedDependency()
510 Latency = updateLatency(*SrcInst, *DstInst, IsArtificial, Latency); in adjustSchedDependency()
541 MachineInstr &DstInst, bool IsArtificial, in updateLatency() argument
637 MachineInstr &DstInst = *Dst->getInstr(); in isBestZeroLatency() local
643 if (SrcInst.isPHI() || DstInst.isPHI()) in isBestZeroLatency()
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| H A D | HexagonSubtarget.h | 364 int updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst,
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MIRYamlMapping.h | 523 unsigned DstInst;
528 return std::tie(SrcInst, SrcOp, DstInst, DstOp) ==
529 std::tie(Other.SrcInst, Other.SrcOp, Other.DstInst, Other.DstOp);
537 YamlIO.mapRequired("dstinst", Sub.DstInst);
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMLatencyMutations.cpp | 558 auto &DstInst = *Dep.getSUnit()->getInstr(); in memoryRAWHazard() local
559 if (!SrcInst.mayStore() || !DstInst.mayLoad()) in memoryRAWHazard()
563 auto DstMO = *DstInst.memoperands().begin(); in memoryRAWHazard()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIRParser.cpp | 530 {Sub.DstInst, Sub.DstOp}, Sub.Subreg); in setupDebugValueTracking()
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