Searched refs:DestSub0 (Results 1 – 3 of 3) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 8294 Register DestSub0 = MRI.createVirtualRegister(NewDestSubRC); in splitScalar64BitUnaryOp() local
8295 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0); in splitScalar64BitUnaryOp()
8304 std::swap(DestSub0, DestSub1); in splitScalar64BitUnaryOp()
8308 .addReg(DestSub0) in splitScalar64BitUnaryOp()
8334 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalarSMulU64() local
8399 BuildMI(MBB, MII, DL, get(AMDGPU::V_MUL_LO_U32_e64), DestSub0) in splitScalarSMulU64()
8414 .addReg(DestSub0) in splitScalarSMulU64()
8443 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalarSMulPseudo() local
8478 BuildMI(MBB, MII, DL, get(AMDGPU::V_MUL_LO_U32_e64), DestSub0) in splitScalarSMulPseudo()
8483 .addReg(DestSub0) in splitScalarSMulPseudo()
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| H A D | SILoadStoreOptimizer.cpp | 2020 Register DestSub0 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass); in computeBase() local
2023 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADD_CO_U32_e64), DestSub0) in computeBase()
2044 .addReg(DestSub0) in computeBase()
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| H A D | SIISelLowering.cpp | 5349 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter() local
5364 BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0) in EmitInstrWithCustomInserter()
5371 .addReg(DestSub0) in EmitInstrWithCustomInserter()
5405 Register DestSub0 = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in EmitInstrWithCustomInserter() local
5435 MachineInstr *LoHalf = BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0) in EmitInstrWithCustomInserter()
5451 .addReg(DestSub0) in EmitInstrWithCustomInserter()
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