Searched refs:Cond0 (Results 1 – 5 of 5) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/SandboxVectorizer/ |
| H A D | Legality.cpp | 119 auto *Cond0 = Sel0->getCondition(); in notVectorizableBasedOnOpcodesAndTypes() local
120 if (VecUtils::getNumLanes(Cond0) != VecUtils::getNumLanes(Sel0)) in notVectorizableBasedOnOpcodesAndTypes()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZAsmPrinter.cpp | 938 int64_t Cond0 = MI.getOperand(1).getImm(); in LowerPATCHABLE_RET() local
941 .addImm(Cond0) in LowerPATCHABLE_RET()
942 .addImm(Cond1 ^ Cond0) in LowerPATCHABLE_RET()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineSelect.cpp | 3487 static bool isSafeToRemoveBitCeilSelect(ICmpInst::Predicate Pred, Value *Cond0, in isSafeToRemoveBitCeilSelect() argument
3542 if (MatchForward(Cond0)) { in isSafeToRemoveBitCeilSelect()
3544 } else if (match(Cond0, m_Add(m_Value(CommonAncestor), m_APInt(C)))) { in isSafeToRemoveBitCeilSelect()
3591 Value *Cond0, *Ctlz, *CtlzOp; in foldBitCeil() local
3592 if (!match(SI.getCondition(), m_ICmp(Pred, m_Value(Cond0), m_APInt(Cond1)))) in foldBitCeil()
3607 !isSafeToRemoveBitCeilSelect(Pred, Cond0, Cond1, CtlzOp, BitWidth, in foldBitCeil()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | DAGCombiner.cpp | 12078 SDValue Cond0, Cond1; in foldVSelectToSignBitSplatMask() local
12080 if (!sd_match(N0, m_OneUse(m_SetCC(m_Value(Cond0), m_Value(Cond1), in foldVSelectToSignBitSplatMask()
12082 VT != Cond0.getValueType()) in foldVSelectToSignBitSplatMask()
12098 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); in foldVSelectToSignBitSplatMask()
12106 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); in foldVSelectToSignBitSplatMask()
12117 SDValue Sra = DAG.getNode(ISD::SRA, DL, VT, Cond0, ShiftAmt); in foldVSelectToSignBitSplatMask()
12216 SDValue Cond0 = N0->getOperand(0); in visitSELECT() local
12221 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond0, in visitSELECT()
12229 SDValue Cond0 = N0->getOperand(0); in visitSELECT() local
12234 return DAG.getNode(ISD::SELECT, DL, N1.getValueType(), Cond0, N1, in visitSELECT()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 47900 SDValue Cond0 = Cond.getOperand(0); in combineSelect() local
47923 if (LHS == Cond0 && RHS == Cond1) { in combineSelect()
47927 Cond = DAG.getSetCC(SDLoc(Cond), CondVT, Cond0, Cond1, NewCC); in combineSelect()
47932 Cond = DAG.getSetCC(SDLoc(Cond), CondVT, Cond0, Cond1, NewCC); in combineSelect()
47950 Cond0 == InnerSetCC.getOperand(0) && in combineSelect()
47963 Cond = DAG.getSetCC(DL, CondVT, Cond0, Cond1, NewCC); in combineSelect()
49160 SDValue Cond0 = Cond.getOperand(0); in combineCMov() local
49161 if (Cond0.getOpcode() == ISD::TRUNCATE) in combineCMov()
49162 Cond0 = Cond0.getOperand(0); in combineCMov()
49164 if (Cond0 == TrueOp && Sub1C && Sub1C->getZExtValue() == 2) { in combineCMov()
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