Searched refs:CLK_TOP_UNIVPLL_D5_D4 (Results 1 – 9 of 9) sorted by relevance
106 #define CLK_TOP_UNIVPLL_D5_D4 70 macro
111 #define CLK_TOP_UNIVPLL_D5_D4 92 macro
81 #define CLK_TOP_UNIVPLL_D5_D4 71 macro
105 #define CLK_TOP_UNIVPLL_D5_D4 93 macro
129 #define CLK_TOP_UNIVPLL_D5_D4 118 macro
162 #define CLK_TOP_UNIVPLL_D5_D4 150 macro
1474 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,1475 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;1580 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,1581 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;1598 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,1599 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
1374 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,1375 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;1450 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,1451 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;1473 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;1489 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;1505 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;1521 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
957 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,958 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;