Searched refs:BaseRegOp (Results 1 – 3 of 3) sorted by relevance
876 const MachineOperand &BaseRegOp = in mergeNarrowZeroStores() local909 .add(BaseRegOp) in mergeNarrowZeroStores()1119 const MachineOperand &BaseRegOp = in mergePairedInsns() local1206 MIB.addReg(BaseRegOp.getReg(), RegState::Define); in mergePairedInsns()1210 .add(BaseRegOp) in mergePairedInsns()
3124 const MachineOperand &BaseRegOp = MemI.getOperand(0); in canFoldIntoAddrMode() local3125 if (BaseRegOp.isReg() && BaseRegOp.getReg() == Reg) in canFoldIntoAddrMode()
3697 const MCOperand &BaseRegOp = Inst.getOperand(StartOp + 1); in expandMem16Inst() local3698 assert(BaseRegOp.isReg() && "expected register operand kind"); in expandMem16Inst()3704 MCRegister BaseReg = BaseRegOp.getReg(); in expandMem16Inst()3825 const MCOperand &BaseRegOp = Inst.getOperand(StartOp + 1); in expandMem9Inst() local3826 assert(BaseRegOp.isReg() && "expected register operand kind"); in expandMem9Inst()3832 MCRegister BaseReg = BaseRegOp.getReg(); in expandMem9Inst()