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/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMicroMipsInstrFPU.td260 let BaseOpcode = "RECIP_D32";
272 let BaseOpcode = "RSQRT_D32";
283 let BaseOpcode = "LDC132";
287 let BaseOpcode = "SDC164";
298 let BaseOpcode = "LDC164";
302 let BaseOpcode = "SDC164";
311 let BaseOpcode = "c.f."#NAME;
316 let BaseOpcode = "c.un."#NAME;
321 let BaseOpcode = "c.eq."#NAME;
326 let BaseOpcode = "c.ueq."#NAME;
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H A DMipsEVAInstrInfo.td61 string BaseOpcode = instr_asm;
79 string BaseOpcode = instr_asm;
96 string BaseOpcode = instr_asm;
114 string BaseOpcode = instr_asm;
130 string BaseOpcode = instr_asm;
144 string BaseOpcode = instr_asm;
174 string BaseOpcode = instr_asm;
H A DMipsDSPInstrInfo.td274 string BaseOpcode = instr_asm;
285 string BaseOpcode = instr_asm;
296 string BaseOpcode = instr_asm;
307 string BaseOpcode = instr_asm;
319 string BaseOpcode = instr_asm;
330 string BaseOpcode = instr_asm;
341 string BaseOpcode = instr_asm;
351 string BaseOpcode = instr_asm;
363 string BaseOpcode = instr_asm;
374 string BaseOpcode = instr_asm;
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H A DMipsInstrFPU.td288 let BaseOpcode = "c.f."#NAME;
293 let BaseOpcode = "c.un."#NAME;
298 let BaseOpcode = "c.eq."#NAME;
303 let BaseOpcode = "c.ueq."#NAME;
308 let BaseOpcode = "c.olt."#NAME;
312 let BaseOpcode = "c.ult."#NAME;
316 let BaseOpcode = "c.ole."#NAME;
320 let BaseOpcode = "c.ule."#NAME;
324 let BaseOpcode = "c.sf."#NAME;
329 let BaseOpcode = "c.ngle."#NAME;
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H A DMicroMips32r6InstrInfo.td616 string BaseOpcode = opstr;
651 string BaseOpcode = instr_asm;
666 string BaseOpcode = opstr;
679 string BaseOpcode = opstr;
690 string BaseOpcode = opstr;
702 string BaseOpcode = opstr;
724 string BaseOpcode = opstr;
737 string BaseOpcode = opstr;
746 string BaseOpcode = opstr;
767 string BaseOpcode = "ldc1";
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H A DMipsDSPInstrFormats.td13 // Instructions with the same BaseOpcode and isNVStore values form a row.
14 let RowFields = ["BaseOpcode"];
49 string BaseOpcode = opstr;
H A DMipsInstrFormats.td42 // Instructions with the same BaseOpcode and isNVStore values form a row.
43 let RowFields = ["BaseOpcode"];
56 // Instructions with the same BaseOpcode and isNVStore values form a row.
57 let RowFields = ["BaseOpcode"];
119 string BaseOpcode = opstr;
H A DMips32r6InstrFormats.td17 // Instructions with the same BaseOpcode and isNVStore values form a row.
18 let RowFields = ["BaseOpcode"];
29 string BaseOpcode = opstr;
H A DMicroMipsInstrInfo.td221 let BaseOpcode = opstr;
232 let BaseOpcode = opstr;
274 string BaseOpcode = opstr;
290 string BaseOpcode = opstr;
588 let BaseOpcode = opstr;
593 let BaseOpcode = opstr;
600 let BaseOpcode = opstr;
607 let BaseOpcode = opstr;
H A DMicroMipsDSPInstrFormats.td13 string BaseOpcode = opstr;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrFMA3Info.cpp158 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in getFMA3Group() local
159 bool IsFMA3Opcode = ((BaseOpcode >= 0x96 && BaseOpcode <= 0x9F) || in getFMA3Group()
160 (BaseOpcode >= 0xA6 && BaseOpcode <= 0xAF) || in getFMA3Group()
161 (BaseOpcode >= 0xB6 && BaseOpcode <= 0xBF)); in getFMA3Group()
185 unsigned FormIndex = ((BaseOpcode - 0x90) >> 4) & 0x3; in getFMA3Group()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DMIMGInstructions.td38 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME);
65 let Fields = ["BaseOpcode", "Store", "Atomic", "AtomicX2", "Sampler",
71 let PrimaryKey = ["BaseOpcode"];
220 MIMGBaseOpcode BaseOpcode;
242 let Fields = ["Opcode", "BaseOpcode", "MIMGEncoding", "VDataDwords",
247 let PrimaryKey = ["BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"];
300 let d16 = !if(BaseOpcode.HasD16, ?, 0);
311 let d16 = !if(BaseOpcode.HasD16, ?, 0);
323 let d16 = !if(BaseOpcode.HasD16, ?, 0);
341 let d16 = !if(BaseOpcode.HasD16, ?, 0);
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H A DAMDGPUInstrInfo.h52 unsigned BaseOpcode; member
87 getImageDimIntrinsicByBaseOpcode(unsigned BaseOpcode, unsigned Dim);
H A DAMDGPUInstCombineIntrinsic.cpp159 AMDGPU::getMIMGLZMappingInfo(ImageDimIntr->BaseOpcode)) { in simplifyAMDGCNImageIntrinsic()
176 AMDGPU::getMIMGMIPMappingInfo(ImageDimIntr->BaseOpcode)) { in simplifyAMDGCNImageIntrinsic()
193 AMDGPU::getMIMGBiasMappingInfo(ImageDimIntr->BaseOpcode)) { in simplifyAMDGCNImageIntrinsic()
211 AMDGPU::getMIMGOffsetMappingInfo(ImageDimIntr->BaseOpcode)) { in simplifyAMDGCNImageIntrinsic()
229 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in simplifyAMDGCNImageIntrinsic() local
230 AMDGPU::getMIMGBaseOpcodeInfo(ImageDimIntr->BaseOpcode); in simplifyAMDGCNImageIntrinsic()
232 if (BaseOpcode->HasD16) { in simplifyAMDGCNImageIntrinsic()
321 AMDGPU::getMIMGBaseOpcodeInfo(ImageDimIntr->BaseOpcode)->Sampler; in simplifyAMDGCNImageIntrinsic()
H A DSIInsertHardClauses.cpp122 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); in getHardClauseType()
H A DAMDGPULegalizerInfo.cpp6458 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in legalizeImageIntrinsic() local
6459 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode); in legalizeImageIntrinsic()
6470 if (!BaseOpcode->NoReturn || BaseOpcode->Store) { in legalizeImageIntrinsic()
6476 (BaseOpcode->BaseOpcode == AMDGPU::IMAGE_ATOMIC_PK_ADD_F16 || in legalizeImageIntrinsic()
6477 BaseOpcode->BaseOpcode == AMDGPU::IMAGE_ATOMIC_PK_ADD_BF16); in legalizeImageIntrinsic()
6485 ST.hasG16() ? (BaseOpcode->Gradients && GradTy == S16) : GradTy == S16; in legalizeImageIntrinsic()
6490 if (!BaseOpcode->Atomic) { in legalizeImageIntrinsic()
6492 if (BaseOpcode->Gather4) { in legalizeImageIntrinsic()
6496 } else if (!IsTFE && !BaseOpcode->Store) { in legalizeImageIntrinsic()
6512 if (BaseOpcode->Store) in legalizeImageIntrinsic()
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H A DAMDGPUInstructionSelector.cpp2034 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in selectImageIntrinsic() local
2035 AMDGPU::getMIMGBaseOpcodeInfo(Intr->BaseOpcode); in selectImageIntrinsic()
2038 unsigned IntrOpcode = Intr->BaseOpcode; in selectImageIntrinsic()
2052 if (!BaseOpcode->Sampler) in selectImageIntrinsic()
2075 if (BaseOpcode->Atomic) { in selectImageIntrinsic()
2081 const bool Is64Bit = BaseOpcode->AtomicX2 ? in selectImageIntrinsic()
2085 if (BaseOpcode->AtomicX2) { in selectImageIntrinsic()
2096 DMaskLanes = BaseOpcode->Gather4 ? 4 : llvm::popcount(DMask); in selectImageIntrinsic()
2098 if (BaseOpcode->Store) { in selectImageIntrinsic()
2102 } else if (BaseOpcode->NoReturn) { in selectImageIntrinsic()
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp1585 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in encodeInstruction() local
1588 BaseOpcode = 0x0F; // Weird 3DNow! encoding. in encodeInstruction()
1606 emitByte(BaseOpcode, CB); in encodeInstruction()
1615 emitByte(BaseOpcode + OpcodeOffset, CB); in encodeInstruction()
1626 emitByte(BaseOpcode, CB); in encodeInstruction()
1632 emitByte(BaseOpcode, CB); in encodeInstruction()
1639 emitByte(BaseOpcode, CB); in encodeInstruction()
1647 emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++)), CB); in encodeInstruction()
1651 emitByte(BaseOpcode, CB); in encodeInstruction()
1671 emitByte(BaseOpcode + CC, CB); in encodeInstruction()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrInfo.td53 let BaseOpcode = "A2_add";
217 let BaseOpcode = "A2_addi";
303 let BaseOpcode = "A2_and";
344 let BaseOpcode = "A2_aslh";
356 let BaseOpcode = "A2_asrh";
430 let BaseOpcode = "A2_combinew";
588 let BaseOpcode = "A2_or";
632 let BaseOpcode = "A2_add";
649 let BaseOpcode = "A2_add";
664 let BaseOpcode = "A2_addi";
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H A DHexagon.td210 // Instructions with the same BaseOpcode and isNVStore values form a row.
211 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"];
226 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
238 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
250 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
262 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
274 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
286 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
368 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
376 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
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H A DHexagonPseudo.td168 let BaseOpcode = "call";
222 BaseOpcode = "PS_call_nr", isExtentSigned = 1, opExtentAlign = 2 in
320 isBarrier = 1, BaseOpcode = "JMPret" in {
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.cpp301 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, in getMIMGOpcode() argument
304 getMIMGOpcodeHelper(BaseOpcode, MIMGEncoding, VDataDwords, VAddrDwords); in getMIMGOpcode()
310 return Info ? getMIMGBaseOpcodeInfo(Info->BaseOpcode) : nullptr; in getMIMGBaseOpcode()
316 getMIMGOpcodeHelper(OrigInfo->BaseOpcode, OrigInfo->MIMGEncoding, in getMaskedMIMGOp()
321 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, in getAddrSizeMIMGOp() argument
324 unsigned AddrWords = BaseOpcode->NumExtraArgs; in getAddrSizeMIMGOp()
325 unsigned AddrComponents = (BaseOpcode->Coordinates ? Dim->NumCoords : 0) + in getAddrSizeMIMGOp()
326 (BaseOpcode->LodOrClampOrMip ? 1 : 0); in getAddrSizeMIMGOp()
337 if (BaseOpcode->Gradients) { in getAddrSizeMIMGOp()
338 if ((IsA16 && !IsG16Supported) || BaseOpcode->G16) in getAddrSizeMIMGOp()
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H A DAMDGPUBaseInfo.h415 MIMGBaseOpcode BaseOpcode; member
439 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
506 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
513 unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
519 uint16_t BaseOpcode; member
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCInstrFormats.td113 string BaseOpcode = "";
500 let BaseOpcode = "ld_rs9";
511 let BaseOpcode = "ld_rs9";
537 let BaseOpcode = "ld_limm";
567 let BaseOpcode = "ld_rlimm";
591 let BaseOpcode = "st_rs9";
602 let BaseOpcode = "st_rs9";
627 let BaseOpcode = "st_limm";
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Disassembler/
H A DAMDGPUDisassembler.cpp1192 const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode = in convertMIMGInst() local
1193 AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode); in convertMIMGInst()
1196 if (BaseOpcode->BVH) { in convertMIMGInst()
1198 addOperand(MI, MCOperand::createImm(BaseOpcode->A16)); in convertMIMGInst()
1219 AMDGPU::getAddrSizeMIMGOp(BaseOpcode, Dim, IsA16, AMDGPU::hasG16(STI)); in convertMIMGInst()
1256 AMDGPU::getMIMGOpcode(Info->BaseOpcode, Info->MIMGEncoding, DstSize, AddrSize); in convertMIMGInst()

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