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Searched refs:BaseOpc (Results 1 – 9 of 9) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrArithmetic.td635 multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4,
643 def 8rr : BinOpRR_RF<BaseOpc, mnemonic, Xi8 , opnodeflag>;
644 def 16rr : BinOpRR_RF<BaseOpc, mnemonic, Xi16, opnodeflag>, OpSize16;
645 def 32rr : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag>, OpSize32;
646 def 64rr : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag>;
649 def 8rr_ND : BinOpRR_RF<BaseOpc, mnemonic, Xi8 , opnodeflag, 1>;
650 def 16rr_ND : BinOpRR_RF<BaseOpc, mnemonic, Xi16, opnodeflag, 1>, PD;
651 def 32rr_ND : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag, 1>;
652 def 64rr_ND : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag, 1>;
653 def 8rr_NF_ND : BinOpRR_R<BaseOpc, mnemonic, Xi8, 1>, EVEX_NF;
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H A DX86FastISel.cpp2909 unsigned BaseOpc, CondCode; in fastLowerIntrinsicCall() local
2913 BaseOpc = ISD::ADD; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2915 BaseOpc = ISD::ADD; CondCode = X86::COND_B; break; in fastLowerIntrinsicCall()
2917 BaseOpc = ISD::SUB; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2919 BaseOpc = ISD::SUB; CondCode = X86::COND_B; break; in fastLowerIntrinsicCall()
2921 BaseOpc = X86ISD::SMUL; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2923 BaseOpc = X86ISD::UMUL; CondCode = X86::COND_O; break; in fastLowerIntrinsicCall()
2938 if (CI->isOne() && (BaseOpc == ISD::ADD || BaseOpc == ISD::SUB) && in fastLowerIntrinsicCall()
2942 bool IsDec = BaseOpc == ISD::SUB; in fastLowerIntrinsicCall()
2947 ResultReg = fastEmit_ri(VT, VT, BaseOpc, LHSReg, CI->getZExtValue()); in fastLowerIntrinsicCall()
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DMatchContext.h87 auto BaseOpc = ISD::getBaseOpcodeForVP(OpVal->getOpcode(), in match() local
89 if (BaseOpc != Opc) in match()
H A DLegalizeVectorTypes.cpp1079 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(N->getOpcode()); in ScalarizeVecOp_VECREDUCE_SEQ() local
1082 return DAG.getNode(BaseOpc, SDLoc(N), N->getValueType(0), in ScalarizeVecOp_VECREDUCE_SEQ()
7674 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Opc); in WidenVecOp_VECREDUCE() local
7675 SDValue NeutralElem = DAG.getNeutralElement(BaseOpc, dl, ElemVT, Flags); in WidenVecOp_VECREDUCE()
7728 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Opc); in WidenVecOp_VECREDUCE_SEQ() local
7729 SDValue NeutralElem = DAG.getNeutralElement(BaseOpc, dl, ElemVT, Flags); in WidenVecOp_VECREDUCE_SEQ()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMLoadStoreOptimizer.cpp701 int BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2ADDspImm in CreateLoadStoreMulti() local
713 BaseOpc = isThumb2 ? (BaseKill && Base == ARM::SP ? ARM::t2SUBspImm in CreateLoadStoreMulti()
736 (BaseOpc == ARM::tADDi8 || BaseOpc == ARM::tSUBi8)) { in CreateLoadStoreMulti()
754 if (BaseOpc == ARM::tADDrSPi) { in CreateLoadStoreMulti()
756 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
761 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
767 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase) in CreateLoadStoreMulti()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/Utils/
H A DAMDGPUBaseInfo.h533 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements);
551 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements);
H A DAMDGPUBaseInfo.cpp468 int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements) { in getMTBUFOpcode() argument
470 getMTBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements); in getMTBUFOpcode()
499 int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements) { in getMUBUFOpcode() argument
501 getMUBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements); in getMUBUFOpcode()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp3241 unsigned BaseOpc = BO.first.getOpcode(); in LowerUnalignedLoad() local
3242 if (BaseOpc == HexagonISD::VALIGNADDR && BO.second % LoadLen == 0) in LowerUnalignedLoad()
3250 SDValue BaseNoOff = (BaseOpc != HexagonISD::VALIGNADDR) in LowerUnalignedLoad()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp11180 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Op.getOpcode()); in lowerVectorMaskVecReduction() local
11181 return DAG.getNode(BaseOpc, DL, Op.getValueType(), SetCC, Op.getOperand(0)); in lowerVectorMaskVecReduction()
11227 unsigned BaseOpc = ISD::getVecReduceBaseOpcode(Op.getOpcode()); in lowerVECREDUCE() local
11235 Vec = DAG.getNode(BaseOpc, DL, VecEVT, Lo, Hi); in lowerVECREDUCE()
11255 SDValue StartV = DAG.getNeutralElement(BaseOpc, DL, VecEltVT, SDNodeFlags()); in lowerVECREDUCE()
11256 switch (BaseOpc) { in lowerVECREDUCE()