Searched refs:BVT (Results 1 – 5 of 5) sorted by relevance
| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 1323 EVT BVT = Ops[I1N].getValueType(); in ppHoistZextI1() local
1326 SDValue C0 = DAG.getConstant(0, dl, BVT); in ppHoistZextI1()
1327 SDValue C1 = DAG.getConstant(1, dl, BVT); in ppHoistZextI1()
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| /freebsd/share/misc/ |
| H A D | iso3166 | 51 BV BVT 074 Bouvet Island
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 6350 EVT BVT = EVT::getVectorVT(*DAG.getContext(), Op0VT, 1); in LowerOperation()
6351 if (!isTypeLegal(BVT)) in LowerOperation()
6353 return DAG.getBitcast(VT, DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, BVT, in LowerOperation()
6354 DAG.getUNDEF(BVT), Op0, in LowerOperation()
6363 EVT BVT = EVT::getVectorVT(*DAG.getContext(), VT, 1); in LowerOperation()
6364 if (!isTypeLegal(BVT)) in LowerOperation()
6366 SDValue BVec = DAG.getBitcast(BVT, Op0); in LowerOperation()
12634 EVT BVT = EVT::getVectorVT(*DAG.getContext(), VT, 1); in ReplaceNodeResults()
12635 if (isTypeLegal(BVT)) { in ReplaceNodeResults()
12636 SDValue BVec = DAG.getBitcast(BVT, Op in ReplaceNodeResults()
6348 EVT BVT = EVT::getVectorVT(*DAG.getContext(), Op0VT, 1); LowerOperation() local
6361 EVT BVT = EVT::getVectorVT(*DAG.getContext(), VT, 1); LowerOperation() local
12631 EVT BVT = EVT::getVectorVT(*DAG.getContext(), VT, 1); ReplaceNodeResults() local
[all...] |
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeIntegerTypes.cpp | 5929 EVT BVT = B.getValueType().getVectorElementType(); in PromoteIntRes_CONCAT_VECTORS() local
5930 return AVT.getScalarSizeInBits() < BVT.getScalarSizeInBits(); in PromoteIntRes_CONCAT_VECTORS()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 19472 EVT BVT = in performConcatVectorsCombine() local
19474 SDValue CC = DAG.getNode(ISD::CONCAT_VECTORS, dl, BVT, X, Y); in performConcatVectorsCombine()
19476 ISD::ADD, dl, BVT, CC, in performConcatVectorsCombine()
19477 DAG.getConstant(1ULL << (N0.getConstantOperandVal(1) - 1), dl, BVT)); in performConcatVectorsCombine()
19479 DAG.getNode(AArch64ISD::VLSHR, dl, BVT, Add, N0.getOperand(1)); in performConcatVectorsCombine()
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