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Searched refs:BH (Results 1 – 25 of 32) sorted by relevance

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/freebsd/contrib/llvm-project/compiler-rt/lib/builtins/hexagon/
H A Ddfaddsub.S15 #define BH r3 macro
80 EXPB = extractu(BH,#EXPBITS,#HI_MANTBITS)
128 B_POS = cmp.gt(BH,#-1)
154 BH = togglebit(BH,#31) define
166 BH = #1 define
170 BH = asl(BH,#31) define
174 if (p0.new) AH = xor(AH,BH)
316 p1 = cmp.gt(BH,#-1)
333 BH = ##0x80000000 define
336 if (!p0) AH = or(AH,BH)
[all …]
H A Ddffma.S19 #define BH r3 macro
147 TMP = xor(AH,BH)
151 EXPB = extractu(BH,#EXPBITS,#HI_MANTBITS)
454 BH = USR define
458 if (p0) BH = or(BH,BL)
461 USR = BH
475 BH = extractu(TMP,#2,#SR_ROUND_OFF) define
480 BH ^= lsr(AH,#31)
481 BL = BH
485 p0 = !cmp.eq(BH,#2)
[all …]
H A Ddfdiv.S16 #define BH r3 macro
81 EXPBA = combine(BH,AH)
82 SIGN = xor(AH,BH)
88 #undef BH
211 #define BH r3 macro
402 EXPBA = combine(BH,AH)
404 BH = insert(TMP,#DF_EXPBITS+1,#DF_MANTBITS-32) // clear out hidden bit, sign bit define
408 if (P_TMP2) BH = or(BH,TMP) // if normal, add back in hidden bit
435 AH = xor(AH,BH)
450 AH = xor(AH,BH)
H A Ddfmul.S14 #define BH r3 macro
114 EXP1 = extractu(BH,#EXPBITS,#HI_MANTBITS)
119 TMP = xor(AH,BH)
400 BH = extract(BH,#1,#31) define
403 AH ^= asl(BH,#31)
/freebsd/contrib/llvm-project/openmp/runtime/src/
H A Dkmp_alloc.cpp151 #define BH(p) ((bhead_t *)(p)) macro
499 ba = BH(((char *)b) + (b->bh.bb.bsize - (bufsize)size)); in bget()
500 bn = BH(((char *)ba) + size); in bget()
532 ba = BH(((char *)b) + b->bh.bb.bsize); in bget()
644 b = BH(buf - sizeof(bhead_t)); in bgetz()
679 b = BH(((char *)buf) - sizeof(bhead_t)); in bgetr()
753 KMP_DEBUG_ASSERT(BH((char *)b - b->bh.bb.bsize)->bb.prevfree == 0); in brel()
770 KMP_DEBUG_ASSERT(BH((char *)b - b->bh.bb.prevfree)->bb.bsize == in brel()
796 KMP_DEBUG_ASSERT(BH((char *)bn + bn->bh.bb.bsize)->bb.prevfree == in brel()
839 KMP_DEBUG_ASSERT(BH((char *)b + b->bh.bb.bsize)->bb.bsize == ESent); in brel()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86RegisterInfo.td61 def BH : X86Reg<"bh", 7>;
190 def BX : X86Reg<"bx", 3, [BL,BH]>;
540 // FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in
546 (add AL, CL, DL, AH, CH, DH, BL, BH, SIL, DIL, BPL, SPL,
550 let AltOrders = [(sub GR8, AH, BH, CH, DH)];
626 def GR8_ABCD_H : RegisterClass<"X86", [i8], 8, (add AH, CH, DH, BH)>;
639 (add AL, CL, DL, AH, CH, DH, BL, BH)> {
640 let AltOrders = [(sub GR8_NOREX, AH, BH, CH, DH)];
660 let AltOrders = [(sub GR8_NOREX2, AH, BH, CH, DH)];
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM55.td204 "t2USA", "t2USUB", "t2UXTA[BH]")>;
213 def : InstRW<[M55WriteCX_DI], (instregex "t2LDR[BH]?i12$", "t2LDRS?[BH]?s$",
226 "tMOVr$", "tUXT[BH]$", "tSXT[BH]$")>;
230 "t2MOVr$", "t2SUBS?ri$", "t2[US]XT[BH]$")>;
H A DARMScheduleR52.td293 "tLDR[BH](r|i|spi|pci|pciASM)", "tLDR(r|i|spi|pci|pciASM)",
491 "RFE", "t2RFE", "t2STR[BH](i12|i8|s)$", "tSTR[BH](i|r)", "tSTR(i|r)", "tSTRspi")>;
496 "STR(BT|HT|T)", "t2STR_(PRE|POST)", "t2STR[BH]_(PRE|POST)",
497 "t2STR_preidx", "t2STR[BH]_preidx", "t2ST(RB|RH|R)T")>;
H A DARMScheduleSwift.td358 "t2LDR(H|B)(i8|i12|s|pci)", "LDREX", "tLDR[BH](r|i|spi|pci|pciASM)",
492 "t2STR(i12|i8|s)$", "t2STR[BH](i12|i8|s)$", "tSTR[BH](i|r)", "tSTR(i|r)", "tSTRspi")>;
497 "STR(BT|HT|T)", "t2STR_(PRE|POST)", "t2STR[BH]_(PRE|POST)",
498 "t2STR_preidx", "t2STR[BH]_preidx", "t2ST(RB|RH|R)T")>;
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp187 {codeview::RegisterId::BH, X86::BH}, in initLLVMToSEHAndCVRegMapping()
782 case X86::BH: \ in getX86SubSuperRegister()
804 B_SUB_SUPER(BH) in getX86SubSuperRegister()
H A DX86MCCodeEmitter.cpp971 if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH) in emitVEXOpcodePrefix()
1353 if (Reg == X86::AH || Reg == X86::BH || Reg == X86::CH || Reg == X86::DH) in emitREXPrefix()
/freebsd/crypto/openssl/test/recipes/04-test_pem_reading_data/
H A Ddsa-threecolumn.pem256 8BH
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedA64FX.td2300 def : InstRW<[A64FXWrite_INDEX_RI_BH], (instregex "^INDEX_(RI|IR)_[BH]")>;
2313 def : InstRW<[A64FXWrite_INDEX_II_BH], (instregex "^INDEX_II_[BH]")>;
2320 def : InstRW<[A64FXWrite_INDEX_RR_BH], (instregex "^INDEX_RR_[BH]")>;
2373 def : InstRW<[A64FXWrite_LD2_BH], (instregex "^LD2[BH]")>;
2394 def : InstRW<[A64FXWrite_LD3_BH], (instregex "^LD3[BH]")>;
2415 def : InstRW<[A64FXWrite_LD4_BH], (instregex "^LD4[BH]")>;
2502 (instregex "^SST1[BH]_S(_[^I]|$)", "^SST1W(_[^ID]|$)")>;
2518 (instregex "^SST1[BH]_S_I", "^SST1W_I")>;
2533 def : InstRW<[A64FXWrite_ST2_BH], (instregex "^ST2[BH]")>;
2554 def : InstRW<[A64FXWrite_ST3_BH], (instregex "^ST3[BH]")>;
[all...]
H A DAArch64SchedA510.td741 def : InstRW<[CortexA510Write<3, CortexA510UnitVALU>], (instregex "^CNT_ZPmZ_[BH]")>;
875 def : InstRW<[CortexA510MCWrite<7, 2, CortexA510UnitVALU>], (instregex "^N?MATCH_PPzZZ_[BH]")>;
1207 "^LDNT1S[BH]_ZZR_S$")>;
1244 def : InstRW<[CortexA510MCWrite<9, 9, CortexA510UnitLdSt>], (instregex "^GLD(FF)?1S?[BH]_S_IMM$",
1264 def : InstRW<[CortexA510MCWrite<7, 7, CortexA510UnitLd>], (instregex "^GLD(FF)?1S?[BH]_S_[SU]XTW$",
1330 def : InstRW<[CortexA510VSt<9>], (instregex "^SST1[BH]_S_IMM$",
1350 def : InstRW<[CortexA510VSt<8>], (instregex "^SST1[BH]_S_[SU]XTW$",
H A DAArch64SchedNeoverseN2.td1793 def : InstRW<[N2Write_2cyc_1V0_1M], (instregex "^N?MATCH_PPzZZ_[BH]$")>;
2124 "^LDNT1S[BH]_ZZR_S$")>;
2161 def : InstRW<[N2Write_9cyc_1L_1V], (instregex "^GLD(FF)?1S?[BH]_S_IMM$",
2181 def : InstRW<[N2Write_9cyc_1L_1V], (instregex "^GLD(FF)?1S?[BH]_S_[SU]XTW$",
2246 def : InstRW<[N2Write_4cyc_2L01_2V], (instregex "^SST1[BH]_S_IMM$",
2266 def : InstRW<[N2Write_4cyc_2L01_2V], (instregex "^SST1[BH]_S_[SU]XTW$",
H A DAArch64SchedNeoverseV2.td2306 def : InstRW<[V2Write_2or3cyc_1V0_1M], (instregex "^N?MATCH_PPzZZ_[BH]")>;
2642 "^LDNT1S[BH]_ZZR_S$")>;
2679 def : InstRW<[V2Write_9cyc_1L_4V], (instregex "^GLD(FF)?1S?[BH]_S_IMM$",
2698 def : InstRW<[V2Write_9cyc_1L_4V], (instregex "^GLD(FF)?1S?[BH]_S_[SU]XTW$",
2761 def : InstRW<[V2Write_4cyc_4L01_4V01], (instregex "^SST1[BH]_S_IMM$",
2781 def : InstRW<[V2Write_4cyc_4L01_4V01], (instregex "^SST1[BH]_S_[SU]XTW$",
H A DAArch64SchedNeoverseV1.td1764 def : InstRW<[V1Write_11c_1L_1V], (instregex "^GLD(FF)?1S?[BH]_S_IMM$",
1781 (instregex "^GLD(FF)?1S?[BH]_S_[SU]XTW$",
1836 def : InstRW<[V1Write_10c_2L01_2V], (instregex "^SST1[BH]_S_IMM$",
1839 "^SST1[BH]_S_[SU]XTW$",
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrFormats.td1538 bits<2> BH;
1545 let Inst{19-20} = BH;
1559 let BH = 0;
1566 let BH = 0;
1574 let BH = 0;
1631 bits<2> BH;
1642 let Inst{19-20} = BH;
1661 let BH = 0;
1679 let Inst{19-20} = 0; // Unused (BH)
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp756 auto [BH, EH] = std::make_pair(std::begin(HvxInts), std::end(HvxInts)); in getIntrinsicId()
762 auto FoundHvx = std::lower_bound(BH, EH, Hvx{Opc, 0, 0}, CmpOpcode); in getIntrinsicId()
/freebsd/share/misc/
H A Diso316638 BH BHR 048 Bahrain
486 # AFGHANISTAN (AF), AZERBAIJAN (AZ), BAHRAIN (BH), BOSNIA AND HERZEGOVINA
/freebsd/contrib/llvm-project/lldb/source/Plugins/SymbolFile/NativePDB/
H A DCodeViewRegisterMapping.cpp661 case llvm::codeview::RegisterId::BH: in GetRegisterSize()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h121 ENTRY(BH) \
/freebsd/contrib/llvm-project/llvm/include/llvm/DebugInfo/CodeView/
H A DCodeViewRegisters.def59 CV_REGISTER(BH, 8)
/freebsd/usr.sbin/tzsetup/
H A Dbaseline64 BH:Bahrain
/freebsd/contrib/tzdata/
H A Dzone.tab81 BH +2623+05035 Asia/Bahrain

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