| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsExpandPseudo.cpp | 85 unsigned BEQ = Mips::BEQ; in expandAtomicCmpSwapSubword() local
93 BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM; in expandAtomicCmpSwapSubword()
166 BuildMI(loop2MBB, DL, TII->get(BEQ)) in expandAtomicCmpSwapSubword()
212 unsigned LL, SC, ZERO, BNE, BEQ, MOVE; in expandAtomicCmpSwap() local
219 BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM; in expandAtomicCmpSwap()
228 BEQ = Mips::BEQ; in expandAtomicCmpSwap()
238 BEQ = Mips::BEQ64; in expandAtomicCmpSwap()
288 BuildMI(loop2MBB, DL, TII->get(BEQ)) in expandAtomicCmpSwap()
311 unsigned BEQ = Mips::BEQ; in expandAtomicBinOpSubword() local
317 BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM; in expandAtomicBinOpSubword()
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| H A D | MipsInstrInfo.cpp | 312 case Mips::BEQ: case Mips::BEQ64: in isBranchOffsetInRange()
470 case Mips::BEQ: in getEquivalentCompactForm()
503 case Mips::BEQ: in getEquivalentCompactForm()
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| H A D | MipsSEInstrInfo.cpp | 475 case Mips::BEQ: return Mips::BNE; in getOppositeBranchOpc()
477 case Mips::BNE: return Mips::BEQ; in getOppositeBranchOpc()
630 return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE || in getAnalyzableBrOpc()
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| H A D | MipsScheduleI6400.td | 86 (instrs J, JAL, JALR, B, BEQ, BNE, BGEZ, BGTZ, BLEZ, BLTZ,
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| H A D | MipsAsmPrinter.cpp | 1208 EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::BEQ) in EmitSled()
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| H A D | MipsInstrInfo.td | 2237 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>,
2261 def B : UncondBranch<BEQ, brtarget>, ISA_MIPS1;
2845 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>,
2855 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>,
3297 defm : BrcondPats<GPR32, BEQ, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>,
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| H A D | MipsScheduleP5600.td | 72 def : InstRW<[P5600WriteJump], (instrs B, BAL, BAL_BR, BEQ, BEQL, BGEZ, BGEZAL,
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaInstrInfo.cpp | 216 case Xtensa::BEQ: in reverseBranchCondition()
220 Cond[0].setImm(Xtensa::BEQ); in reverseBranchCondition()
284 case Xtensa::BEQ: in getBranchDestBlock()
321 case Xtensa::BEQ: in isBranchOffsetInRange()
569 case Xtensa::BEQ: in insertConstBranchAtInst()
633 case Xtensa::BEQ: in insertBranchAtInst()
685 case Xtensa::BEQ: in isBranch()
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| H A D | XtensaISelLowering.cpp | 821 return Xtensa::BEQ; in getBranchOpcode()
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| /freebsd/contrib/llvm-project/compiler-rt/lib/xray/ |
| H A D | xray_trampoline_arm.S | 29 BEQ FunctionEntry_restore
61 BEQ FunctionExit_restore
92 BEQ FunctionTailExit_restore
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVRedundantCopyElimination.cpp | 76 if (Opc == RISCV::BEQ && Cond[2].isReg() && Cond[2].getReg() == RISCV::X0 && in guaranteesZeroRegInBlock()
142 assert((CondBr->getOpcode() == RISCV::BEQ || in optimizeBlock()
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| H A D | RISCVInstrInfo.cpp | 963 case RISCV::BEQ: in getCondFromBranchOpc()
1037 return RISCV::BEQ; in getBrCond()
1365 case RISCV::BEQ: in reverseBranchCondition()
1369 Cond[0].setImm(RISCV::BEQ); in reverseBranchCondition()
1473 case RISCV::BEQ: in optimizeCondBranch()
1500 unsigned NewOpc = evaluateCondBranch(CC, C0, C1) ? RISCV::BEQ : RISCV::BNE; in optimizeCondBranch()
1614 case RISCV::BEQ: in isBranchOffsetInRange()
4290 case RISCV::BEQ: in simplifyInstruction()
4314 MI.setDesc(get(RISCV::BEQ)); in simplifyInstruction()
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| H A D | RISCVAsmPrinter.cpp | 710 MCInstBuilder(RISCV::BEQ) in LowerKCFI_CHECK()
852 MCInstBuilder(RISCV::BEQ) in EmitHwasanMemaccessSymbols()
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| H A D | RISCVInstrInfoC.td | 969 def : CompressPat<(BEQ GPRC:$rs1, X0, bare_simm9_lsb0:$imm),
972 def : CompressPat<(BEQ X0, GPRC:$rs1, bare_simm9_lsb0:$imm),
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| H A D | RISCVInstrInfo.td | 749 def BEQ : BranchCC_rri<0b000, "beq">;
1052 (BEQ GPR:$rs, X0, bare_simm13_lsb0:$offset)>;
1696 defm : BccPat<SETEQ, BEQ>;
1704 def : BrccCompressOpt<SETEQ, BEQ>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchExpandAtomicPseudoInsts.cpp | 229 BuildMI(LoopMBB, DL, TII->get(LoongArch::BEQ)) in doAtomicBinOpExpansion()
312 BuildMI(LoopMBB, DL, TII->get(LoongArch::BEQ)) in doMaskedAtomicBinOpExpansion()
482 BuildMI(LoopTailMBB, DL, TII->get(LoongArch::BEQ)) in expandAtomicMinMaxOp()
558 BuildMI(LoopTailMBB, DL, TII->get(LoongArch::BEQ)) in expandAtomicCmpXchg()
599 BuildMI(LoopTailMBB, DL, TII->get(LoongArch::BEQ)) in expandAtomicCmpXchg()
708 BuildMI(LoopTailMBB, DL, TII->get(LoongArch::BEQ)) in expandAtomicCmpXchg128()
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| H A D | LoongArchISelDAGToDAG.h | 76 return LoongArch::BEQ; in getBranchOpcForIntCC()
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| H A D | LoongArchInstrInfo.cpp | 363 case LoongArch::BEQ: in isBranchOffsetInRange()
686 case LoongArch::BEQ: in getOppositeBranchOpc()
689 return LoongArch::BEQ; in getOppositeBranchOpc()
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| H A D | LoongArchInstrInfo.td | 842 def BEQ : BrCC_2RI16<0x58000000>;
1544 def : BccPat<seteq, BEQ>;
1578 (BEQ GPR:$rj, R0, bb:$imm16)>;
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/MCTargetDesc/ |
| H A D | RISCVAsmBackend.cpp | 152 return RISCV::BEQ; in getRelaxedOpcode()
186 case RISCV::BEQ: in getRelaxedOpcode()
277 case RISCV::BEQ: in relaxInstruction()
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| H A D | RISCVMCCodeEmitter.cpp | 253 return RISCV::BEQ; in getInvertedBranchOp()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/ |
| H A D | LoongArchMCCodeEmitter.cpp | 186 case LoongArch::BEQ: in getExprOpValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/ |
| H A D | MipsInstPrinter.cpp | 273 case Mips::BEQ: in printAlias()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/ |
| H A D | MipsAsmParser.cpp | 1849 case Mips::BEQ: in processInstruction()
2054 BInst.setOpcode(inMicroMipsMode() ? Mips::BEQ_MM : Mips::BEQ); in processInstruction()
3644 OpCode = Mips::BEQ; in expandBranchImm()
4075 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO, in expandCondBranches()
4100 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO, in expandCondBranches()
4118 TOut.emitRRX(AcceptsEquality ? Mips::BEQ : Mips::BNE, in expandCondBranches()
4161 : (AcceptsEquality ? Mips::BEQ : Mips::BNE), in expandCondBranches()
5219 TOut.emitRRX(Mips::BEQ, DstReg, ATReg, LabelOp, IDLoc, STI); in expandMulO()
5256 TOut.emitRRX(Mips::BEQ, ATReg, Mips::ZERO, LabelOp, IDLoc, STI); in expandMulOU()
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| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/ |
| H A D | EmulateInstructionRISCV.cpp | 49 constexpr uint32_t BEQ = 0b000; variable
170 case BEQ: in CompareB()
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