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Searched refs:AL_FIELD_MASK (Results 1 – 12 of 12) sorted by relevance

/freebsd/sys/contrib/alpine-hal/
H A Dal_hal_unit_adapter_regs.h185 #define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_COMP_STAT_MASK AL_FIELD_MASK(1, 0)
187 #define AL_ADAPTER_AXI_MSTR_RD_WR_ERR_ATTR_MSTR_ID_MASK AL_FIELD_MASK(4, 2)
214 #define AL_ADAPTER_AXI_MSTR_TO_WR_MASK AL_FIELD_MASK(31, 16)
216 #define AL_ADAPTER_AXI_MSTR_TO_RD_MASK AL_FIELD_MASK(15, 0)
268 #define AL_ADPTR_GEN_CTL_12_SATA_AWUSER_VAL_MASK AL_FIELD_MASK(15, 0)
270 #define AL_ADPTR_GEN_CTL_12_SATA_AWUSER_SEL_MASK AL_FIELD_MASK(31, 16)
273 #define AL_ADPTR_GEN_CTL_13_SATA_ARUSER_VAL_MASK AL_FIELD_MASK(15, 0)
275 #define AL_ADPTR_GEN_CTL_13_SATA_ARUSER_SEL_MASK AL_FIELD_MASK(31, 16)
283 #define AL_ADPTR_GEN_CTL_14_SATA_VM_ARADDR_SEL_MASK AL_FIELD_MASK(13, 8)
286 #define AL_ADPTR_GEN_CTL_14_SATA_VM_AWADDR_SEL_MASK AL_FIELD_MASK(21, 16)
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H A Dal_hal_pcie_regs.h406 #define PCIE_PORT_GEN2_CTRL_NUM_OF_LANES_MASK AL_FIELD_MASK(12, 8)
419 #define PCIE_PORT_LINK_CTRL_LINK_CAPABLE_MASK AL_FIELD_MASK(21, 16)
429 #define PCIE_PORT_GEN3_MAX_FUNC_NUM AL_FIELD_MASK(7, 0)
436 #define PCIE_FLT_MASK_SKP_INT_VAL_MASK AL_FIELD_MASK(10, 0)
467 #define RADM_PQ_HCRD_VC0_MASK AL_FIELD_MASK(19, 12)
471 #define RADM_NPQ_HCRD_VC0_MASK AL_FIELD_MASK(19, 12)
475 #define RADM_CPLQ_HCRD_VC0_MASK AL_FIELD_MASK(19, 12)
486 #define PCIE_IATU_CR1_FUNC_NUM_MASK AL_FIELD_MASK(24, 20)
505 #define PCIE_PORT_DEV_CTRL_STATUS_MPS_MASK AL_FIELD_MASK(7, 5)
509 #define PCIE_PORT_DEV_CTRL_STATUS_MRRS_MASK AL_FIELD_MASK(14, 12)
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H A Dal_hal_serdes_hssp_internal_regs.h523 #define SERDES_IREG_FLD_RXELECIDLE_SIGDETTHRESH_MASK AL_FIELD_MASK(2, 0)
527 #define SERDES_IREG_FLD_RXLOSDET_THRESH_MASK AL_FIELD_MASK(4, 3)
682 #define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_MASK AL_FIELD_MASK(5, 4)
H A Dal_hal_serdes_internal_regs.h524 #define SERDES_IREG_FLD_RXELECIDLE_SIGDETTHRESH_MASK AL_FIELD_MASK(2, 0)
528 #define SERDES_IREG_FLD_RXLOSDET_THRESH_MASK AL_FIELD_MASK(4, 3)
683 #define SERDES_IREG_FLD_PCS_VPCSIF_OVR_RATE_MASK AL_FIELD_MASK(5, 4)
H A Dal_hal_pcie_axi_reg.h697 #define PCIE_AXI_DEVICE_ID_REG_DEV_ID_MASK AL_FIELD_MASK(31, 16)
701 #define PCIE_AXI_DEVICE_ID_REG_REV_ID_MASK AL_FIELD_MASK(15, 0)
982 #define PCIE_AXI_STATUS_LANE_REQUESTED_SPEED_MASK AL_FIELD_MASK(2, 0)
1024 #define PCIE_AXI_POS_ORDER_9_8 AL_FIELD_MASK(9, 8)
H A Dal_hal_reg_utils.h103 #define AL_FIELD_MASK(msb, lsb) \ macro
H A Dal_hal_serdes_hssp.c3047 (params->ppm_drift_count & AL_FIELD_MASK(7, 0)) >> 0); in al_serdes_sris_config()
3050 (params->ppm_drift_count & AL_FIELD_MASK(15, 8)) >> 8); in al_serdes_sris_config()
3054 (params->ppm_drift_max & AL_FIELD_MASK(7, 0)) >> 0); in al_serdes_sris_config()
3057 (params->ppm_drift_max & AL_FIELD_MASK(15, 8)) >> 8); in al_serdes_sris_config()
3061 (params->synth_ppm_drift_max & AL_FIELD_MASK(7, 0)) >> 0); in al_serdes_sris_config()
3064 (params->synth_ppm_drift_max & AL_FIELD_MASK(15, 8)) >> 8); in al_serdes_sris_config()
H A Dal_hal_udma.h157 #define AL_UDMA_CDESC_BUF2_LEN_MASK AL_FIELD_MASK(29, 16)
H A Dal_hal_serdes_25g.c692 buf[(y * x_samples) + x] |= (data[byte] & AL_FIELD_MASK(msb, lsb) >> lsb); in al_serdes_25g_eye_diag_run()
H A Dal_hal_pcie.c644 AL_FIELD_MASK(26, 25) | AL_FIELD_MASK(31, 28), 0); in al_pcie_port_pf_params_config()
/freebsd/sys/contrib/alpine-hal/eth/
H A Dal_hal_eth_main.c2856 AL_REG_FIELD_SET(val, AL_FIELD_MASK(3,0), 0, entry->prio_sel); in al_eth_fwd_ctrl_entry_to_val()
2857 AL_REG_FIELD_SET(val, AL_FIELD_MASK(7,4), 4, entry->queue_sel_1); in al_eth_fwd_ctrl_entry_to_val()
2858 AL_REG_FIELD_SET(val, AL_FIELD_MASK(9,8), 8, entry->queue_sel_2); in al_eth_fwd_ctrl_entry_to_val()
2859 AL_REG_FIELD_SET(val, AL_FIELD_MASK(13,10), 10, entry->udma_sel); in al_eth_fwd_ctrl_entry_to_val()
2860 AL_REG_FIELD_SET(val, AL_FIELD_MASK(17,15), 15, entry->hdr_split_len_sel); in al_eth_fwd_ctrl_entry_to_val()
2882 && (index->protocol_id != AL_REG_FIELD_GET(i, AL_FIELD_MASK(8,4),4))) in al_eth_ctrl_index_match()
2885 && (index->mac_type != AL_REG_FIELD_GET(i, AL_FIELD_MASK(10,9),9))) in al_eth_ctrl_index_match()
3049 AL_REG_FIELD_SET(val, AL_FIELD_MASK(3,0), 0, udma_mask); in al_eth_fwd_mhash_table_set()
3050 AL_REG_FIELD_SET(val, AL_FIELD_MASK(5,4), 4, qid); in al_eth_fwd_mhash_table_set()
3061 AL_REG_FIELD_SET(val, AL_FIELD_MASK(5,2), 2, entry->udma_mask); in al_eth_fwd_vid_entry_to_val()
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H A Dal_hal_eth.h346 #define AL_ETH_RX_FLAGS_TGTID_MASK AL_FIELD_MASK(15, 0)
361 #define AL_ETH_RX_FLAGS_SW_SRC_PORT_MASK AL_FIELD_MASK(15, 13)
363 #define AL_ETH_RX_FLAGS_LRO_CONTEXT_VAL_MASK AL_FIELD_MASK(10, 3)
365 #define AL_ETH_RX_FLAGS_L4_OFFSET_MASK AL_FIELD_MASK(10, 3)
367 #define AL_ETH_RX_FLAGS_PRIORITY_MASK AL_FIELD_MASK(2, 0)