Searched hist:fbd1cec57064aa1380726ec899c49fcd84e702b9 (Results 1 – 3 of 3) sorted by relevance
| /linux/arch/arc/plat-axs10x/ |
| H A D | axs10x.c | diff fbd1cec57064aa1380726ec899c49fcd84e702b9 Sat Dec 09 14:59:17 CET 2017 Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> ARC: [plat-axs103]: Set initial core pll output frequency
Set initial core pll output frequency specified in device tree to
100MHz for SMP configuration and 90MHz for UP configuration.
It will be applied at the core pll driver probing.
Update platform quirk for decreasing core frequency for quad core
configuration.
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
|
| /linux/arch/arc/boot/dts/ |
| H A D | axc003_idu.dtsi | diff fbd1cec57064aa1380726ec899c49fcd84e702b9 Sat Dec 09 14:59:17 CET 2017 Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> ARC: [plat-axs103]: Set initial core pll output frequency
Set initial core pll output frequency specified in device tree to
100MHz for SMP configuration and 90MHz for UP configuration.
It will be applied at the core pll driver probing.
Update platform quirk for decreasing core frequency for quad core
configuration.
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
|
| H A D | axc003.dtsi | diff fbd1cec57064aa1380726ec899c49fcd84e702b9 Sat Dec 09 14:59:17 CET 2017 Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> ARC: [plat-axs103]: Set initial core pll output frequency
Set initial core pll output frequency specified in device tree to
100MHz for SMP configuration and 90MHz for UP configuration.
It will be applied at the core pll driver probing.
Update platform quirk for decreasing core frequency for quad core
configuration.
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
|