Searched hist:ec8f7f3342c88780d682cc2464daf0fe43259c4f (Results 1 – 2 of 2) sorted by relevance
| /linux/arch/arm/include/asm/ |
| H A D | arch_timer.h | diff ec8f7f3342c88780d682cc2464daf0fe43259c4f Sun Oct 17 14:42:19 CEST 2021 Marc Zyngier <maz@kernel.org> clocksource/drivers/arm_arch_timer: Drop unnecessary ISB on CVAL programming
Switching from TVAL to CVAL has a small drawback: we need an ISB
before reading the counter. We cannot get rid of it, but we can
instead remove the one that comes just after writing to CVAL.
This reduces the number of ISBs from 3 to 2 when programming
the timer.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-12-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
| /linux/arch/arm64/include/asm/ |
| H A D | arch_timer.h | diff ec8f7f3342c88780d682cc2464daf0fe43259c4f Sun Oct 17 14:42:19 CEST 2021 Marc Zyngier <maz@kernel.org> clocksource/drivers/arm_arch_timer: Drop unnecessary ISB on CVAL programming
Switching from TVAL to CVAL has a small drawback: we need an ISB
before reading the counter. We cannot get rid of it, but we can
instead remove the one that comes just after writing to CVAL.
This reduces the number of ISBs from 3 to 2 when programming
the timer.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211017124225.3018098-12-maz@kernel.org
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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