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/linux/drivers/gpu/drm/msm/dsi/ |
H A D | dsi.h | diff 34d9545b9f769c6553e31a6820c9cb51f5e93099 Wed Jul 29 18:14:12 CEST 2015 Archit Taneja <architt@codeaurora.org> drm/msm/dsi: Reset both PHYs before clock operation for dual DSI
In case of dual DSI, some registers in PHY1 have been programmed during PLL0 clock's set_rate. The PHY1 reset called by host1 later will silently reset those PHY1 registers. This change is to reset and enable both PHYs before any PLL clock operation.
[Originally worked on by Hai Li <hali@codeaurora.org>. Fixed up by Archit Taneja <architt@codeaurora.org>]
Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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H A D | dsi_manager.c | diff 34d9545b9f769c6553e31a6820c9cb51f5e93099 Wed Jul 29 18:14:12 CEST 2015 Archit Taneja <architt@codeaurora.org> drm/msm/dsi: Reset both PHYs before clock operation for dual DSI
In case of dual DSI, some registers in PHY1 have been programmed during PLL0 clock's set_rate. The PHY1 reset called by host1 later will silently reset those PHY1 registers. This change is to reset and enable both PHYs before any PLL clock operation.
[Originally worked on by Hai Li <hali@codeaurora.org>. Fixed up by Archit Taneja <architt@codeaurora.org>]
Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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H A D | dsi_host.c | diff 34d9545b9f769c6553e31a6820c9cb51f5e93099 Wed Jul 29 18:14:12 CEST 2015 Archit Taneja <architt@codeaurora.org> drm/msm/dsi: Reset both PHYs before clock operation for dual DSI
In case of dual DSI, some registers in PHY1 have been programmed during PLL0 clock's set_rate. The PHY1 reset called by host1 later will silently reset those PHY1 registers. This change is to reset and enable both PHYs before any PLL clock operation.
[Originally worked on by Hai Li <hali@codeaurora.org>. Fixed up by Archit Taneja <architt@codeaurora.org>]
Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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