Searched hist:"33707260422475385 c6f33f526c71805a3dc5dab" (Results 1 – 3 of 3) sorted by relevance
| /linux/drivers/clk/mvebu/ |
| H A D | mv98dx3236.c | 33707260422475385c6f33f526c71805a3dc5dab Tue Feb 07 21:28:15 CET 2017 Chris Packham <chris.packham@alliedtelesis.co.nz> clk: mvebu: Expand mv98dx3236-core-clock support
The initial implementation in commit e120c17a70e5 ("clk: mvebu: support
for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency.
Port code from the Marvell supplied Linux kernel to support different
PLL frequencies and provide clock gating support.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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| H A D | armada-xp.c | diff 33707260422475385c6f33f526c71805a3dc5dab Tue Feb 07 21:28:15 CET 2017 Chris Packham <chris.packham@alliedtelesis.co.nz> clk: mvebu: Expand mv98dx3236-core-clock support
The initial implementation in commit e120c17a70e5 ("clk: mvebu: support
for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency.
Port code from the Marvell supplied Linux kernel to support different
PLL frequencies and provide clock gating support.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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| H A D | Makefile | diff 33707260422475385c6f33f526c71805a3dc5dab Tue Feb 07 21:28:15 CET 2017 Chris Packham <chris.packham@alliedtelesis.co.nz> clk: mvebu: Expand mv98dx3236-core-clock support
The initial implementation in commit e120c17a70e5 ("clk: mvebu: support
for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency.
Port code from the Marvell supplied Linux kernel to support different
PLL frequencies and provide clock gating support.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
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