Searched full:zen1 (Results 1 – 4 of 4) sorted by relevance
240 * SRSO untraining sequence for Zen1/2, similar to retbleed_untrain_ret()307 * The SRSO Zen1/2 (MOVABS) untraining sequence is longer than the314 * must all start at a cacheline boundary for Zen1/2 generations. That
891 * certain circumstances on Zen1/2 uarch, and not all parts have had in fix_erratum_1386()940 pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n"); in init_amd_zen1()953 pr_notice_once("AMD Zen1 FPDSS bug detected, enabling mitigation.\n"); in init_amd_zen1()
2964 /* Zen1/2 with SMT off aren't vulnerable to SRSO. */ in srso_select_mitigation()
309 #define X86_FEATURE_ZEN1 (11*32+31) /* CPU based on Zen1 microarchitecture */