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/linux/arch/powerpc/lib/
H A Dxor_vmx.c1 // SPDX-License-Identifier: GPL-2.0-or-later
44 #define XOR(V1, V2) \ macro
46 V1##_0 = vec_xor(V1##_0, V2##_0); \
47 V1##_1 = vec_xor(V1##_1, V2##_1); \
48 V1##_2 = vec_xor(V1##_2, V2##_2); \
49 V1##_3 = vec_xor(V1##_3, V2##_3); \
57 DEFINE(v2); in __xor_altivec_2()
62 LOAD(v2); in __xor_altivec_2()
63 XOR(v1, v2); in __xor_altivec_2()
67 v2 += 4; in __xor_altivec_2()
[all …]
H A Dmemcpy_power7.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
26 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
40 clrldi r6,r6,(64-3)
65 stdu r1,-STACKFRAMESIZE(r1)
119 clrldi r5,r5,(64-7)
178 9: clrldi r5,r5,(64-4)
207 15: ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
217 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
218 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
220 stdu r1,-STACKFRAMESIZE(r1)
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/linux/Documentation/devicetree/bindings/dma/
H A Dmarvell,xor-v2.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/dma/marvell,xor-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Marvell XOR v2 engines
10 - Andrew Lunn <andrew@lunn.ch>
15 - const: marvell,xor-v2
16 - items:
17 - enum:
18 - marvell,armada-7k-xor
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/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap810-ap0.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
15 interrupt-parent = <&gic>;
23 compatible = "arm,psci-0.2";
28 compatible = "arm,armv8-timer";
36 #address-cells = <2>;
37 #size-cells = <2>;
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H A Darmada-ap80x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/thermal/thermal.h>
11 /dts-v1/;
14 #address-cells = <2>;
15 #size-cells = <2>;
25 compatible = "arm,psci-0.2";
29 reserved-memory {
30 #address-cells = <2>;
31 #size-cells = <2>;
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/linux/lib/crc/powerpc/
H A Dcrc-vpmsum-template.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 * 32 bits of 0s to the end - this matches what a CRC does. We just
28 #include <asm/ppc-opcode.h>
66 std r31,-8(r1)
67 std r30,-16(r1)
68 std r29,-24(r1)
69 std r28,-32(r1)
70 std r27,-40(r1)
71 std r26,-48(r1)
72 std r25,-56(r1)
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/linux/arch/arm64/crypto/
H A Daes-ce-ccm-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aes-ce-ccm-core.S - AES-CCM transform for ARMv8 with Crypto Extensions
5 * Copyright (C) 2013 - 2017 Linaro Ltd.
15 .arch armv8-a+crypto
20 ld1 {v10.4s-v13.4s}, [\rk]
21 ld1 {v14.4s-v17.4s}, [\tmp], #64
22 ld1 {v18.4s-v21.4s}, [\tmp], #64
23 ld1 {v3.4s-v5.4s}, [\tmp]
65 ld1 {v2.16b}, [x1], #16 /* load next input block */
67 eor v2.16b, v2.16b, v5.16b /* final round enc+mac */
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H A Daes-modes.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * linux/arch/arm64/crypto/aes-modes.S - chaining mode wrappers for AES
5 * Copyright (C) 2013 - 2017 Linaro Ltd <ard.biesheuvel@linaro.org>
8 /* included by aes-ce.S and aes-neon.S */
26 encrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
31 decrypt_block4x v0, v1, v2, v3, w3, x2, x8, w7
37 encrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
42 decrypt_block5x v0, v1, v2, v3, v4, w3, x2, x8, w7
62 ld1 {v0.16b-v3.16b}, [x1], #64 /* get 4 pt blocks */
66 st1 {v0.16b-v3.16b}, [x0], #64
[all …]
H A Daes-neonbs-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
10 * 'Faster and Timing-Attack Resistant AES-GCM' by Emilia Kaesper and
14 * for 32-bit ARM written by Andy Polyakov <appro@openssl.org>
216 ldp q18, q19, [bskey, #-96]
217 ldp q20, q21, [bskey, #-64]
218 ldp q22, q23, [bskey, #-32]
222 ldp q16, q17, [bskey, #-128]!
407 cmtst v2.16b, v7.16b, v10.16b
420 stp q2, q3, [x0, #-96]
421 stp q4, q5, [x0, #-64]
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/linux/lib/crc/s390/
H A Dcrc32le-vx.c1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Hardware-accelerated CRC-32 variants for Linux on z Systems
6 * computing of bitreflected CRC-32 checksums for IEEE 802.3 Ethernet
9 * This CRC-32 implementation algorithm is bitreflected and processes
10 * the least-significant bit first (Little-Endian).
18 #include "crc32-vx.h"
20 /* Vector register range containing CRC-32 constants */
29 * The CRC-32 constant block contains reduction constants to fold and
32 * For the CRC-32 variants, the constants are precomputed according to
36 * R2 = [(x4*128-32 mod P'(x) << 32)]' << 1
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H A Dcrc32be-vx.c1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Hardware-accelerated CRC-32 variants for Linux on z Systems
6 * computing of CRC-32 checksums.
8 * This CRC-32 implementation algorithm processes the most-significant
17 #include "crc32-vx.h"
19 /* Vector register range containing CRC-32 constants */
28 * The CRC-32 constant block contains reduction constants to fold and
31 * For the CRC-32 variants, the constants are precomputed according to
49 * can be multiplied by 1 to perform an XOR without the need for a separate
52 * CRC-32 (IEEE 802.3 Ethernet, ...) polynomials:
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/linux/arch/x86/crypto/
H A Daes-xts-avx-x86_64.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // AES-XTS for modern x86_64 CPUs
9 //------------------------------------------------------------------------------
11 // This file is dual-licensed, meaning that you can use it under your choice of
17 // http://www.apache.org/licenses/LICENSE-2.0
50 * This file implements AES-XTS for modern x86_64 CPUs. To handle the
55 * AES-NI && AVX
56 * - 128-bit vectors (1 AES block per vector)
57 * - VEX-coded instructions
58 * - xmm0-xmm15
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H A Daes-ctr-avx-x86_64.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
7 // This file is dual-licensed, meaning that you can use it under your choice of
13 // http://www.apache.org/licenses/LICENSE-2.0
45 //------------------------------------------------------------------------------
47 // This file contains x86_64 assembly implementations of AES-CTR and AES-XCTR
49 // - AES-NI && AVX
50 // - VAES && AVX2
51 // - VAES && AVX512BW && AVX512VL && BMI2
95 // Broadcast a 128-bit value from memory to all 128-bit lanes of a vector
107 // XOR two vectors together.
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/linux/arch/arm64/lib/
H A Dxor-neon.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * arch/arm64/lib/xor-neon.c
9 #include <linux/raid/xor.h>
11 #include <asm/neon-intrinsics.h>
19 register uint64x2_t v0, v1, v2, v3; in xor_arm64_neon_2() local
26 v2 = veorq_u64(vld1q_u64(dp1 + 4), vld1q_u64(dp2 + 4)); in xor_arm64_neon_2()
32 vst1q_u64(dp1 + 4, v2); in xor_arm64_neon_2()
37 } while (--lines > 0); in xor_arm64_neon_2()
48 register uint64x2_t v0, v1, v2, v3; in xor_arm64_neon_3() local
55 v2 = veorq_u64(vld1q_u64(dp1 + 4), vld1q_u64(dp2 + 4)); in xor_arm64_neon_3()
[all …]
/linux/lib/crc/
H A Dcrc32-main.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * cleaned up code to current version of sparse and added the slicing-by-8
5 * algorithm to the closely similar existing slicing-by-4 algorithm.
10 * subsequently included in the kernel, thus was re-licensed under the
11 * GNU GPL v2.
17 * Some xor at the end with ~0. The generic crc32() function takes
18 * seed as an argument, and doesn't xor at the end. Then individual
20 * drivers/net/smc9194.c uses seed ~0, doesn't xor with ~0.
21 * fs/jffs2 uses seed 0, doesn't xor with ~0.
22 * fs/partitions/efi.c uses seed ~0, xor's with ~0.
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/linux/lib/crc/arm64/
H A Dcrc-t10dif-core.S2 // Accelerated CRC-T10DIF using arm64 NEON and Crypto Extensions instructions
5 // Copyright (C) 2019-2024 Google LLC
17 // Implement fast CRC-T10DIF computation with SSE and PCLMULQDQ instructions
65 // /white-papers/fast-crc-computation-generic-polynomials-pclmulqdq-paper.pdf
72 .arch armv8-a+crypto
96 * Pairwise long polynomial multiplication of two 16-bit values
100 * by two 64-bit values
128 * and after performing 8x8->16 bit long polynomial multiplication of
130 * we obtain the following four vectors of 16-bit elements:
138 * matching ranks. Then, the final XOR (*) can be pulled forward, and
[all …]
/linux/lib/raid6/
H A Drvv.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * RAID-6 syndrome calculation using RISC-V vector instructions
9 * Copyright 2002-2004 H. Peter Anvin
30 z0 = disks - 3; /* Highest data disk */ in raid6_rvv1_gen_syndrome_real()
31 p = dptr[z0 + 1]; /* XOR parity */ in raid6_rvv1_gen_syndrome_real()
41 /* v0:wp0, v1:wq0, v2:wd0/w20, v3:w10 */ in raid6_rvv1_gen_syndrome_real()
53 for (z = z0 - 1 ; z >= 0 ; z--) { in raid6_rvv1_gen_syndrome_real()
65 "vsra.vi v2, v1, 7\n" in raid6_rvv1_gen_syndrome_real()
67 "vand.vx v2, v2, %[x1d]\n" in raid6_rvv1_gen_syndrome_real()
68 "vxor.vv v3, v3, v2\n" in raid6_rvv1_gen_syndrome_real()
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H A Dvpermxor.uc11 * Based on H. Peter Anvin's paper - The mathematics of RAID-6
13 * $#-way unrolled portable integer math RAID-6 instruction set
20 * This instruction was introduced in POWER8 - ISA v2.07.
27 #include <asm/ppc-opcode.h>
51 z0 = disks - 3; /* Highest data disk */
52 p = dptr[z0+1]; /* XOR parity */
58 for (z = z0-1; z>=0; z--) {
/linux/arch/loongarch/lib/
H A Dxor_template.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Template for XOR operations, instantiated in xor_simd.c.
9 * - LINE_WIDTH
10 * - XOR_FUNC_NAME(nr)
11 * - LD_INOUT_LINE(buf)
12 * - LD_AND_XOR_LINE(buf)
13 * - ST_LINE(buf)
18 const unsigned long * __restrict v2)
25 LD_AND_XOR_LINE(v2)
27 : : [v1] "r"(v1), [v2] "r"(v2) : "memory"
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/linux/arch/riscv/crypto/
H A Dsm4-riscv64-zvksed-zvkb.S1 /* SPDX-License-Identifier: Apache-2.0 OR BSD-2-Clause */
3 // This file is dual-licensed, meaning that you can use it under your
40 // The generated code of this file depends on the following RISC-V extensions:
41 // - RV64I
42 // - RISC-V Vector ('V') with VLEN >= 128
43 // - RISC-V Vector SM4 Block Cipher extension ('Zvksed')
44 // - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
60 // XOR the user key with the family key.
62 vle32.v v2, (t0)
63 vxor.vv v1, v1, v2
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/linux/lib/crypto/powerpc/
H A Dchacha-p10le-8x.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
16 # row1 = (row1 + row2), row4 = row1 xor row4, row4 rotate each word by 16
17 # row3 = (row3 + row4), row2 = row3 xor row2, row2 rotate each word by 12
18 # row1 = (row1 + row2), row4 = row1 xor row4, row4 rotate each word by 8
19 # row3 = (row3 + row4), row2 = row3 xor row2, row2 rotate each word by 7
35 # Column round (v0, v4, v8, v12, v1, v5, v9, v13, v2, v6, v10, v14, v3, v7, v11, v15)
36 # Diagnal round (v0, v5, v10, v15, v1, v6, v11, v12, v2, v7, v8, v13, v3, v4, v9, v14)
40 #include <asm/asm-offsets.h>
41 #include <asm/asm-compat.h>
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/linux/drivers/input/keyboard/
H A Djornada680_kbd.c1 // SPDX-License-Identifier: GPL-2.0-only
43 /* PTD1 */ KEY_CAPSLOCK, KEY_MACRO, KEY_LEFTCTRL, 0, KEY_ESC, KEY_KP5, 0, 0, /* 1 -> 8 */
44 KEY_F1, KEY_F2, KEY_F3, KEY_F8, KEY_F7, KEY_F6, KEY_F4, KEY_F5, /* 9 -> 16 */
45 /* PTD5 */ KEY_SLASH, KEY_APOSTROPHE, KEY_ENTER, 0, KEY_Z, 0, 0, 0, /* 17 -> 24 */
46 KEY_X, KEY_C, KEY_V, KEY_DOT, KEY_COMMA, KEY_M, KEY_B, KEY_N, /* 25 -> 32 */
47 /* PTD7 */ KEY_KP2, KEY_KP6, KEY_KP3, 0, 0, 0, 0, 0, /* 33 -> 40 */
48 …KEY_F10, KEY_RO, KEY_F9, KEY_KP4, KEY_NUMLOCK, KEY_SCROLLLOCK, KEY_LEFTALT, KEY_HANJA, /* 41 -> 4…
49 /* PTE0 */ KEY_KATAKANA, KEY_KP0, KEY_GRAVE, 0, KEY_FINANCE, 0, 0, 0, /* 49 -> 56 */
50 KEY_KPMINUS, KEY_HIRAGANA, KEY_SPACE, KEY_KPDOT, KEY_VOLUMEUP, 249, 0, 0, /* 57 -> 64 */
51 /* PTE1 */ KEY_SEMICOLON, KEY_RIGHTBRACE, KEY_BACKSLASH, 0, KEY_A, 0, 0, 0, /* 65 -> 72 */
[all …]
/linux/lib/crypto/arm64/
H A Dchacha-neon-core.S4 * Copyright (C) 2016-2018 Linaro, Ltd. <ard.biesheuvel@linaro.org>
11 * ChaCha20 256-bit cipher algorithm, RFC7539, x64 SSSE3 functions
29 * chacha_permute - permute one block
31 * Permute one 64-byte block where the state matrix is stored in the four NEON
32 * registers v0-v3. It performs matrix operations on four words in parallel,
51 add v2.4s, v2.4s, v3.4s
52 eor v4.16b, v1.16b, v2.16b
62 add v2.4s, v2.4s, v3.4s
63 eor v4.16b, v1.16b, v2.16b
70 ext v2.16b, v2.16b, v2.16b, #8
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/linux/drivers/clk/imx/
H A Dclk.c1 // SPDX-License-Identifier: GPL-2.0
4 #include <linux/clk-provider.h>
66 struct clk *clk = ERR_PTR(-ENODEV); in imx_obtain_fixed_clock_from_dt()
71 return ERR_PTR(-ENOMEM); in imx_obtain_fixed_clock_from_dt()
125 return ERR_PTR(-ENOENT); in imx_get_clk_hw_by_name()
147 * That's why we do the xor operation below.
230 MODULE_LICENSE("GPL v2");
/linux/tools/testing/selftests/powerpc/copyloops/
H A Dmemcpy_power7.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
26 std r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
40 clrldi r6,r6,(64-3)
65 stdu r1,-STACKFRAMESIZE(r1)
119 clrldi r5,r5,(64-7)
178 9: clrldi r5,r5,(64-4)
207 15: ld r3,-STACKFRAMESIZE+STK_REG(R31)(r1)
217 std r4,-STACKFRAMESIZE+STK_REG(R30)(r1)
218 std r5,-STACKFRAMESIZE+STK_REG(R29)(r1)
220 stdu r1,-STACKFRAMESIZE(r1)
[all …]

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