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173 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */174 #define SPRN_PWRMGTCR0 0x3FB /* Power management control register 0 */
664 #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
100 unsigned char dmapad4[0x3fb];
1127 #define LOONGARCH_CSR_IB13ASID 0x3fb /* inst breakpoint 13 asid */
5708 #define mmXDMA_PG_STATUS 0x3fb
7211 #define mmXDMA_PG_STATUS 0x3fb
7511 #define mmXDMA_PG_STATUS 0x3fb
8904 #define mmXDMA_PG_STATUS 0x3fb