Home
last modified time | relevance | path

Searched +full:wakeup +full:- +full:pin (Results 1 – 25 of 377) sorted by relevance

12345678910>>...16

/linux/Documentation/devicetree/bindings/net/
H A Dmarvell-bt-8xxx.txt2 ------
9 - compatible : should be one of the following:
10 * "marvell,sd8897-bt" (for SDIO)
11 * "marvell,sd8997-bt" (for SDIO)
16 - marvell,cal-data: Calibration data downloaded to the device during
20 - marvell,wakeup-pin: It represents wakeup pin number of the bluetooth chip.
21 firmware will use the pin to wakeup host system (u16).
22 - marvell,wakeup-gap-ms: wakeup gap represents wakeup latency of the host
25 - interrupt-names: Used only for USB based devices (See below)
26 - interrupts : specifies the interrupt pin number to the cpu. For SDIO, the
[all …]
/linux/Documentation/devicetree/bindings/net/bluetooth/
H A Dnxp,88w8987-bt.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/bluetooth/nxp,88w8987-bt.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 This binding describes UART-attached NXP bluetooth chips. These chips
11 are dual-radio chips supporting WiFi and Bluetooth. The bluetooth
12 works on standard H4 protocol over 4-wire UART. The RTS and CTS lines
14 asserts break signal over UART-TX line to put the chip into power save
15 state. De-asserting break wakes up the BT chip.
18 - Neeraj Sanjay Kale <neeraj.sanjaykale@nxp.com>
[all …]
H A Dbrcm,bluetooth.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
13 This binding describes Broadcom UART-attached bluetooth chips.
18 - items:
19 - enum:
20 - infineon,cyw43439-bt
21 - const: brcm,bcm4329-bt
22 - enum:
[all …]
/linux/drivers/pinctrl/freescale/
H A Dpinctrl-scu.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2018 NXP
16 #include "pinctrl-imx.h"
20 #define IMX_SC_IRQ_GROUP_WAKE 3 /* Wakeup interrupts */
21 #define IMX_SC_IRQ_PAD 2 /* Pad wakeup */
47 u8 wakeup; member
68 hdr->ver = IMX_SC_RPC_VERSION; in imx_pinconf_get_scu()
69 hdr->svc = IMX_SC_RPC_SVC_PAD; in imx_pinconf_get_scu()
70 hdr->func = IMX_SC_PAD_FUNC_GET; in imx_pinconf_get_scu()
71 hdr->size = 2; in imx_pinconf_get_scu()
[all …]
/linux/arch/arm64/boot/dts/exynos/
H A Dexynosautov9-sadk.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
16 compatible = "samsung,exynosautov9-sadk", "samsung,exynosautov9";
18 #address-cells = <2>;
19 #size-cells = <2>;
26 stdout-path = &serial_0;
36 gpio-keys {
37 compatible = "gpio-keys";
[all …]
H A Dexynos8895-dreamlte.dts1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Samsung Galaxy S8 (dreamlte/SM-G950F) device tree source
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/soc/samsung,exynos-usi.h>
16 model = "Samsung Galaxy S8 (SM-G950F)";
18 chassis-type = "handset";
25 #address-cells = <2>;
[all …]
H A Dexynosautov920-sadk.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include "exynos-pinctrl.h"
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/input/input.h>
17 compatible = "samsung,exynosautov920-sadk", "samsung,exynosautov920";
19 #address-cells = <2>;
20 #size-cells = <2>;
27 stdout-path = &serial_0;
30 gpio-keys {
[all …]
/linux/Documentation/devicetree/bindings/pinctrl/
H A Dste,nomadik.txt4 - compatible: "stericsson,db8500-pinctrl", "stericsson,db8540-pinctrl",
5 "stericsson,stn8815-pinctrl"
6 - nomadik-gpio-chips: array of phandles to the corresponding GPIO chips
7 (these have the register ranges used by the pin controller).
8 - prcm: phandle to the PRCMU managing the back end of this pin controller
10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 ST Ericsson's pin configuration nodes act as a container for an arbitrary number of
16 pin, a group, or a list of pins or groups. This configuration can include the
17 mux function to select on those pin(s)/group(s), and various pin configuration
[all …]
H A Dmarvell,dove-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
23 uart1(cts), lcd-spi(cs1), pmu*
31 mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
39 mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
41 ac97-1(sysclko)
44 mpp20 20 gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
46 mpp21 21 gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
[all …]
/linux/Documentation/arch/arm/pxa/
H A Dmfp.rst7 MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
15 mechanism is introduced from PXA3xx to completely move the pin-mux functions
16 out of the GPIO controller. In addition to pin-mux configurations, the MFP
17 also controls the low power state, driving strength, pull-up/down and event
18 detection of each pin. Below is a diagram of internal connections between
21 +--------+
22 | |--(GPIO19)--+
24 | |--(GPIO...) |
25 +--------+ |
26 | +---------+
[all …]
/linux/Documentation/devicetree/bindings/soc/ti/
H A Dwkup-m3-ipc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/ti/wkup-m3-ipc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Wakeup M3 IPC device
10 - Dave Gerlach <d-gerlach@ti.com>
11 - Drew Fustini <dfustini@baylibre.com>
14 The TI AM33xx and AM43xx family of devices use a small Cortex M3 co-processor
15 (commonly referred to as Wakeup M3 or CM3) to help with various low power tasks
17 C-states for CPU Idle. Once the wkup_m3_ipc driver uses the wkup_m3_rproc driver
[all …]
/linux/Documentation/devicetree/bindings/input/
H A Dnvidia,tegra20-kbc.txt2 The key controller has maximum 24 pins to make matrix keypad. Any pin
3 can be configured as row or column. The maximum column pin can be 8
7 - compatible: "nvidia,tegra20-kbc"
8 - reg: Register base address of KBC.
9 - interrupts: Interrupt number for the KBC.
10 - nvidia,kbc-row-pins: The KBC pins which are configured as row. This is an
11 array of pin numbers which is used as rows.
12 - nvidia,kbc-col-pins: The KBC pins which are configured as column. This is an
13 array of pin numbers which is used as column.
14 - linux,keymap: The keymap for keys as described in the binding document
[all …]
/linux/drivers/pinctrl/samsung/
H A Dpinctrl-s3c64xx.c1 // SPDX-License-Identifier: GPL-2.0+
3 // S3C64xx specific support for pinctrl-samsung driver.
7 // Based on pinctrl-exynos.c, please see the file for original copyrights.
11 // external gpio and wakeup interrupt support.
24 #include "pinctrl-samsung.h"
31 /* External GPIO and wakeup interrupt related definitions */
116 .eint_mask = (1 << (pins)) - 1, \
140 .eint_mask = (1 << (pins)) - 1, \
194 .eint_mask = (1 << (pins)) - 1, \
200 * struct s3c64xx_eint0_data - EINT0 common data
[all …]
/linux/Documentation/devicetree/bindings/regulator/
H A Drichtek,rtmv20-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
15 (Enable/Fail), Enable pin to turn chip on, and Fail pin as fault indication.
27 wakeup-source: true
32 enable-gpios:
36 richtek,ld-pulse-delay-us:
38 load current pulse delay in microsecond after strobe pin pulse high.
[all …]
/linux/Documentation/devicetree/bindings/rtc/
H A Dingenic,rtc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ingenic SoCs Real-Time Clock
10 - Paul Cercueil <paul@crapouillou.net>
13 - $ref: rtc.yaml#
14 - if:
20 - ingenic,jz4770-rtc
21 - ingenic,jz4780-rtc
24 "#clock-cells": false
[all …]
/linux/arch/arm64/boot/dts/exynos/google/
H A Dgs101-pixel-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree nodes common for all GS101-based Pixel
5 * Copyright 2021-2023 Google LLC
6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/usb/pd.h>
14 #include "gs101-pinctrl.h"
25 stdout-path = &serial_0;
[all …]
/linux/Documentation/devicetree/bindings/gnss/
H A Dsirfstar.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Johan Hovold <johan@kernel.org>
23 - $ref: gnss-common.yaml#
24 - $ref: /schemas/serial/serial-peripheral-props.yaml#
29 - csr,gsd4t
30 - csr,csrg05ta03-icje-r
31 - fastrax,uc430
32 - linx,r4
[all …]
/linux/arch/arm/boot/dts/samsung/
H A Dexynos5250-spring.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
10 #include <dt-bindings/clock/samsung,s2mps11.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/input/input.h>
19 chassis-type = "laptop";
33 stdout-path = "serial3:115200n8";
36 gpio-keys {
37 compatible = "gpio-keys";
[all …]
H A Dexynos5250-snow-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/maxim,max77686.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/sound/samsung-i2s.h>
30 stdout-path = "serial3:115200n8";
33 gpio-keys {
34 compatible = "gpio-keys";
35 pinctrl-names = "default";
[all …]
H A Dexynos4210-universal_c210.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
12 /dts-v1/;
14 #include <dt-bindings/gpio/gpio.h>
19 chassis-type = "handset";
35 stdout-path = "serial2:115200n8";
39 fixed-rate-clocks {
41 compatible = "samsung,clock-xxti";
42 clock-frequency = <0>;
46 compatible = "samsung,clock-xusbxti";
[all …]
/linux/Documentation/devicetree/bindings/input/touchscreen/
H A Dsis_i2c.txt4 - compatible: must be "sis,9200-ts"
5 - reg: i2c slave address
6 - interrupts: touch controller interrupt (see interrupt
10 - pinctrl-names: should be "default" (see pinctrl binding [1]).
11 - pinctrl-0: a phandle pointing to the pin settings for the
13 - attn-gpios: the gpio pin used as attention line
14 - reset-gpios: the gpio pin used to reset the controller
15 - wakeup-source: touchscreen can be used as a wakeup source
17 [0]: Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
18 [1]: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
[all …]
/linux/Documentation/admin-guide/
H A Dbtmrvl.rst14 bit 8:0 -- Gap
15 bit 16:8 -- GPIO
17 where GPIO is the pin number of GPIO used to wake up the host.
18 It could be any valid GPIO pin# (e.g. 0-7) or 0xff (SDIO interface
19 wakeup will be used instead).
21 where Gap is the gap in milli seconds between wakeup signal and
22 wakeup event, or 0xff for special host sleep setting.
30 # Use GPIO pin #3 to wake up the host and set GAP to 0xff:
39 1 -- Enable auto sleep mode
40 0 -- Disable auto sleep mode
[all …]
/linux/drivers/gpio/
H A Dgpio-sama5d2-piobu.c1 // SPDX-License-Identifier: GPL-2.0
26 * wakeup signal generation
53 * sama5d2_piobu_setup_pin() - prepares a pin for set_direction call
55 * Do not consider pin for tamper detection (normal and backup modes)
56 * Do not consider pin as tamper wakeup interrupt source
58 static int sama5d2_piobu_setup_pin(struct gpio_chip *chip, unsigned int pin) in sama5d2_piobu_setup_pin() argument
63 unsigned int mask = BIT(PIOBU_DET_OFFSET + pin); in sama5d2_piobu_setup_pin()
65 ret = regmap_update_bits(piobu->regmap, PIOBU_BMPR, mask, 0); in sama5d2_piobu_setup_pin()
69 ret = regmap_update_bits(piobu->regmap, PIOBU_NMPR, mask, 0); in sama5d2_piobu_setup_pin()
73 return regmap_update_bits(piobu->regmap, PIOBU_WKPR, mask, 0); in sama5d2_piobu_setup_pin()
[all …]
H A Dgpiolib-acpi-quirks.c1 // SPDX-License-Identifier: GPL-2.0
17 #include "gpiolib-acpi.h"
19 static int run_edge_events_on_boot = -1;
22 "Run edge _AEI event-handlers at boot: 0=no, 1=yes, -1=auto");
27 "controller@pin combos on which to ignore the ACPI wake flag "
28 "ignore_wake=controller@pin[,controller@pin[,...]]");
33 "controller@pin combos on which to ignore interrupt "
34 "ignore_interrupt=controller@pin[,controller@pin[,...]]");
77 unsigned int pin; in acpi_gpio_in_ignore_list() local
98 len = pin_str - controller; in acpi_gpio_in_ignore_list()
[all …]
/linux/arch/arm64/boot/dts/renesas/
H A Drenesas-smarc2.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the RZ SMARC Carrier-II Board.
13 * 0 - SMARC SDIO signal is connected to uSD1
14 * 1 - SMARC SDIO signal is connected to M.2 Key E connector
20 * 0 - Connect to GPIO8 PMOD (default)
21 * 1 - Connect to CAN0 transceiver STB pin
24 * 0 - Connect to GPIO9 PMOD (default)
25 * 1 - Connect to CAN1 transceiver STB pin
32 model = "Renesas RZ SMARC Carrier-II Board";
33 compatible = "renesas,smarc2-evk";
[all …]

12345678910>>...16