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/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
25 # Polarity negative negative
28 mode "640x480-60"
31 timings 39722 48 16 33 10 96 2 endmode mode "480x640-60"
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
50 # Polarity negative negative
52 mode "640x480-75"
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
71 # Polarity negative negative
73 mode "640x480-85"
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H A Dpxafb.rst10 modprobe pxafb options=vmem:2M,mode:640x480-8,passive
14 video=pxafb:vmem:2M,mode:640x480-8,passive
21 mode:XRESxYRES[-BPP]
45 vsynclen:VSYNC == LCCR2_VSW + 1
65 hsync:HSYNC, vsync:VSYNC
68 high.
74 outputen:POLARITY
76 Output Enable Polarity. 0 => active low, 1 => active high
78 pixclockpol:POLARITY
80 pixel clock polarity
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H A Dmatroxfb.rst16 * Most important: boot logo :-)
34 box) and matroxfb (for graphics mode). You should not compile-in vesafb
35 unless you have primary display on non-Matrox VBE2.0 device (see
43 -------------
58 -------------------------
73 ----------
86 Non-listed number can be achieved by more complicated command-line, for
93 XF{68,86}_FBDev should work just fine, but it is non-accelerated. On non-intel
97 Running another (accelerated) X-Server like XF86_SVGA works too. But (at least)
100 driver is possible, but you must not enable DRI - if you do, resolution and
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/linux/Documentation/devicetree/bindings/regulator/
H A Drichtek,rtmv20-regulator.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/richtek,rtmv20-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - ChiYuan Huang <cy_huang@richtek.com>
16 There're still four pins for camera control, two inputs (strobe and vsync),
18 supply, vsync input from IR camera, and fsin1/fsin2 output for the optional.
27 wakeup-source: true
32 enable-gpios:
36 richtek,ld-pulse-delay-us:
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/linux/include/media/i2c/
H A Dtvp7002.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
6 * Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
19 * struct tvp7002_config - Platform dependent data
20 *@clk_polarity: Clock polarity
21 * 0 - Data clocked out on rising edge of DATACLK signal
22 * 1 - Data clocked out on falling edge of DATACLK signal
23 *@hs_polarity: HSYNC polarity
24 * 0 - Active low HSYNC output, 1 - Active high HSYNC output
25 *@vs_polarity: VSYNC Polarity
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/linux/arch/sh/include/asm/
H A Dsh7760fb.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sh7760fb.h -- platform data for SH7760/SH7763 LCDC framebuffer driver.
5 * (c) 2006-2008 MSC Vertriebsges.m.b.H.,
19 /* The LCDC dma engine always sets bits 27-26 to 1: this is Area3 */
75 /* HSYNC polarity inversion */
78 /* VSYNC polarity inversion */
81 /* DISPLAY-ENABLE polarity inversion */
84 /* DISPLAY DATA BUS polarity inversion */
90 /* Disable output of HSYNC during VSYNC period */
93 /* Disable output of VSYNC during VSYNC period */
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/linux/Documentation/devicetree/bindings/display/samsung/
H A Dsamsung,exynos5-dp.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos5-dp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Inki Dae <inki.dae@samsung.com>
11 - Seung-Woo Kim <sw0312.kim@samsung.com>
12 - Kyungmin Park <kyungmin.park@samsung.com>
13 - Krzysztof Kozlowski <krzk@kernel.org>
17 const: samsung,exynos5-dp
25 clock-names:
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/linux/drivers/gpu/drm/amd/display/dc/
H A Ddc_hw_types.h41 * Note: do *not* add any types which are *not* used for HW programming - this
245 * in cases such as Stereo 3D, Planar YUV, etc. Other per-flip attributes such
395 * 0x0 - DISPLAY_MICRO_TILING
396 * 0x1 - THIN_MICRO_TILING
397 * 0x2 - DEPTH_MICRO_TILING
398 * 0x3 - ROTATED_MICRO_TILING
560 * enum dc_cursor_color_format - DC cursor programming mode
600 * divided into a high and low parts.
783 it is positive polarity --reversed with dal1 or video bios define*/
785 it is positive polarity --reversed with dal1 or video bios define*/
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/linux/drivers/regulator/
H A Drtmv20-regulator.c1 // SPDX-License-Identifier: GPL-2.0+
75 gpiod_set_value(priv->enable_gpio, 1); in rtmv20_lsw_enable()
80 /* HW re-enable, disable cache only and sync regcache here */ in rtmv20_lsw_enable()
81 regcache_cache_only(priv->regmap, false); in rtmv20_lsw_enable()
82 ret = regcache_sync(priv->regmap); in rtmv20_lsw_enable()
99 regcache_cache_only(priv->regmap, true); in rtmv20_lsw_disable()
100 regcache_mark_dirty(priv->regmap); in rtmv20_lsw_disable()
102 gpiod_set_value(priv->enable_gpio, 0); in rtmv20_lsw_disable()
113 return -EINVAL; in rtmv20_lsw_set_current_limit()
118 sel = (max_uA - RTMV20_LSW_MINUA) / RTMV20_LSW_STEPUA; in rtmv20_lsw_set_current_limit()
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/linux/drivers/gpu/drm/meson/
H A Dmeson_venc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 * - CVBS Encoding via the ENCI encoder and VDAC digital to analog converter
26 * - TMDS/HDMI Encoding via ENCI_DIV and ENCP
27 * - Setup of more clock rates for HDMI modes
31 * - LCD Panel encoding via ENCL
32 * - TV Panel encoding via ENCT
39 * vd1---| |-| | | VENC /---------|----VDAC
40 * vd2---| VIU |-| VPP |-|-----ENCI/-ENCI_DVI-|-|
41 * osd1--| |-| | | \ | X--HDMI-TX
42 * osd2--|_____|-|_____| | |\-ENCP--ENCP_DVI-|-|
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/linux/drivers/gpu/drm/
H A Ddrm_modes.c2 * Copyright © 1997-2003 by The XFree86 Project, Inc.
4 * Copyright © 2007-2008 Intel Corporation
6 * Copyright 2005-2006 Luc Verhaegen
53 * drm_mode_debug_printmodeline - print a mode to dmesg
65 * drm_mode_create - create a new display mode
87 * drm_mode_destroy - remove a mode
103 * drm_mode_probed_add - add a mode to a connector's probed_mode list
114 WARN_ON(!mutex_is_locked(&connector->dev->mode_config.mutex)); in drm_mode_probed_add()
116 list_add_tail(&mode->head, &connector->probed_modes); in drm_mode_probed_add()
127 * - https://web.archive.org/web/20220406232708/http://www.kolumbus.fi/pami1/video/pal_ntsc.html
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/linux/drivers/media/i2c/
H A Dtw9910.c1 // SPDX-License-Identifier: GPL-2.0
13 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
26 #include <linux/v4l2-mediabus.h>
30 #include <media/v4l2-subdev.h>
45 #define CROP_HI 0x07 /* Cropping Register, High */
52 #define SCALE_HI 0x0E /* Scaling Register, High */
136 #define IFSEL_S 0x10 /* 01 : S-video decoding */
146 /* 1 : ITU-R-656 compatible data sequence format */
147 #define LEN 0x40 /* 0 : 8-bit YCrCb 4:2:2 output format */
148 /* 1 : 16-bit YCrCb 4:2:2 output format.*/
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H A Dks0127.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * for the Matrox Marvel G200,G400 and Rainbow Runner-G series
20 * V1.1 Gerard v.d. Horst Added some debugoutput, reset the video-standard
31 #include <media/v4l2-device.h>
234 table[KS_HSCLH] = 0x00; /* Horizontal Scaling Ratio High */ in init_reg_defaults()
236 table[KS_VSCLH] = 0x00; /* Vertical Scaling Ratio High */ in init_reg_defaults()
250 table[KS_UVOFFH] = 0x00; /* UV Offset Adjustment High */ in init_reg_defaults()
257 table[KS_POLCTL] = 0x41; /* Timing Signal Polarity Control */ in init_reg_defaults()
273 /* Command Register F, update -immediately- */ in init_reg_defaults()
274 /* (there might come no vsync)*/ in init_reg_defaults()
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H A Dadv7183.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <media/v4l2-ctrls.h>
20 #include <media/v4l2-device.h>
38 * All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8.
69 return &container_of(ctrl->handler, struct adv7183, hdl)->sd; in to_sd()
95 return -1; in adv7183_writeregs()
165 v4l2_info(sd, "adv7183: Vsync field control 1 2 and 3 = 0x%02x 0x%02x 0x%02x\n", in adv7183_log_status()
173 v4l2_info(sd, "adv7183: Polarity = 0x%02x\n", in adv7183_log_status()
185 v4l2_ctrl_handler_log_status(&decoder->hdl, sd->name); in adv7183_log_status()
193 *std = decoder->std; in adv7183_g_std()
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H A Dov2640.c1 // SPDX-License-Identifier: GPL-2.0-only
9 * Copyright 2005-2009 Freescale Semiconductor, Inc. All Rights Reserved.
20 #include <linux/v4l2-mediabus.h>
23 #include <media/v4l2-device.h>
24 #include <media/v4l2-event.h>
25 #include <media/v4l2-subdev.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-image-sizes.h>
124 * 0: High byte first YUYV (C2[4]=0)
161 #define GAIN 0x00 /* AGC - Gain control gain setting */
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H A Dov9650.c1 // SPDX-License-Identifier: GPL-2.0-only
24 #include <media/media-entity.h>
25 #include <media/v4l2-async.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-device.h>
28 #include <media/v4l2-event.h>
29 #include <media/v4l2-image-sizes.h>
30 #include <media/v4l2-subdev.h>
31 #include <media/v4l2-mediabus.h>
35 MODULE_PARM_DESC(debug, "Debug level (0-2)");
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H A Dtvp5150.c1 // SPDX-License-Identifier: GPL-2.0
3 // tvp5150 - Texas Instruments TVP5150A/AM1 and TVP5151 video decoder driver
7 #include <dt-bindings/media/tvp5150.h>
18 #include <media/v4l2-async.h>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-event.h>
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/v4l2-mc.h>
24 #include <media/v4l2-rect.h>
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/linux/drivers/media/pci/tw5864/
H A Dtw5864-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
147 /* DDR-DPR Burst Read Enable */
157 * 0 Single R/W Access (Host <-> DDR)
158 * 1 Burst R/W Access (Host <-> DPR)
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/linux/drivers/media/usb/gspca/
H A Dsonixb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2009-2011 Jean-François Moine <http://moinejf.free.fr>
14 0x10 high nibble red gain low nibble blue gain
17 0x05 red gain 0-127
18 0x06 blue gain 0-127
19 0x07 green gain 0-127
21 0x08-0x0f i2c / 3wire registers
24 0x15 hsize (hsize = register-value * 16)
25 0x16 vsize (vsize = register-value * 16)
27 0x18 bit 7 enables compression, bit 4-5 set image down scaling:
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H A Dov519.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2008-2011 Jean-François Moine <moinejf@free.fr>
8 * This module is adapted from the ov51x-jpeg package, which itself
13 * Copyright (c) 1999-2006 Mark W. McClelland
20 * ov51x-jpeg original copyright is:
22 * Copyright (c) 2004-2007 Romain Beauxis <toots@rastageeks.org>
38 MODULE_AUTHOR("Jean-Francois Moine <http://moinejf.free.fr>");
482 /*jfm: this value does not work for 800x600 - see isoc_init */
539 #define OV7670_R14_COM9 0x14 /* Control 9 - gain ceiling */
541 #define OV7670_R17_HSTART 0x17 /* Horiz start high bits */
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/linux/drivers/video/fbdev/
H A Damifb.c2 * linux/drivers/video/amifb.c -- Amiga builtin chipset frame buffer device
4 * Copyright (C) 1995-2003 Geert Uytterhoeven
30 * - 24 Jul 96: Copper generates now vblank interrupt and
32 * - 14 Jul 96: Rework and hopefully last ECS bugs fixed
33 * - 7 Mar 96: Hardware sprite support by Roman Zippel
34 * - 18 Feb 96: OCS and ECS support by Roman Zippel
36 * - 2 Dec 95: AGA version by Geert Uytterhoeven
107 ---------------------
111 +----------+---------------------------------------------+----------+-------+
115 +----------###############################################----------+-------+
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/linux/drivers/video/fbdev/omap2/omapfb/displays/
H A Dpanel-dsi-cm.c1 // SPDX-License-Identifier: GPL-2.0-only
92 ddata->hw_guard_wait = msecs_to_jiffies(guard_msec); in hw_guard_start()
93 ddata->hw_guard_end = jiffies + ddata->hw_guard_wait; in hw_guard_start()
98 unsigned long wait = ddata->hw_guard_end - jiffies; in hw_guard_wait()
100 if ((long)wait > 0 && time_before_eq(wait, ddata->hw_guard_wait)) { in hw_guard_wait()
108 struct omap_dss_device *in = ddata->in; in dsicm_dcs_read_1()
112 r = in->ops.dsi->dcs_read(in, ddata->channel, dcs_cmd, buf, 1); in dsicm_dcs_read_1()
124 struct omap_dss_device *in = ddata->in; in dsicm_dcs_write_0()
125 return in->ops.dsi->dcs_write(in, ddata->channel, &dcs_cmd, 1); in dsicm_dcs_write_0()
130 struct omap_dss_device *in = ddata->in; in dsicm_dcs_write_1()
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/linux/drivers/gpu/drm/bridge/
H A Dsamsung-dsim.c1 // SPDX-License-Identifier: GPL-2.0-only
19 #include <linux/media-bus-format.h>
27 #include <drm/bridge/samsung-dsim.h>
114 #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16)
115 #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0)
503 * downstream driver - drivers/gpu/drm/bridge/sec-dsim.c
538 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in samsung_dsim_write()
543 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in samsung_dsim_read()
548 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) in samsung_dsim_wait_for_reset()
551 dev_err(dsi->dev, "timeout waiting for reset\n"); in samsung_dsim_wait_for_reset()
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/linux/drivers/gpu/drm/gma500/
H A Dpsb_intel_reg.h1 /* SPDX-License-Identifier: GPL-2.0-only */
70 #define GMBUS3 0x510c /* data buffer bytes 3-0 */
155 * - PLL enabled
156 * - pipe enabled
157 * - LVDS/DVOB/DVOC on
256 * in DVO non-gang */
413 * Programmed value is multiplier - 1, up to 5x.
442 /* Selects pipe B for LVDS data. Must be set on pre-965. */
449 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
471 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
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/linux/drivers/gpu/drm/radeon/
H A Devergreen.c62 spin_lock_irqsave(&rdev->cg_idx_lock, flags); in eg_cg_rreg()
65 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); in eg_cg_rreg()
73 spin_lock_irqsave(&rdev->cg_idx_lock, flags); in eg_cg_wreg()
76 spin_unlock_irqrestore(&rdev->cg_idx_lock, flags); in eg_cg_wreg()
84 spin_lock_irqsave(&rdev->pif_idx_lock, flags); in eg_pif_phy0_rreg()
87 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); in eg_pif_phy0_rreg()
95 spin_lock_irqsave(&rdev->pif_idx_lock, flags); in eg_pif_phy0_wreg()
98 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); in eg_pif_phy0_wreg()
106 spin_lock_irqsave(&rdev->pif_idx_lock, flags); in eg_pif_phy1_rreg()
109 spin_unlock_irqrestore(&rdev->pif_idx_lock, flags); in eg_pif_phy1_rreg()
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