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/linux/arch/powerpc/kernel/ptrace/
H A Dptrace-altivec.c11 * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
13 * corresponding vector registers. Quadword 32 contains the vscr as the
39 * vector128 vscr;
53 BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) != in vr_get()
75 * vector128 vscr;
87 BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) != in vr_set()
H A Dptrace-tm.c338 * vector128 vscr;
349 BUILD_BUG_ON(TVSO(vscr) != TVSO(vr[32])); in tm_cvmx_get()
389 * vector128 vscr;
399 BUILD_BUG_ON(TVSO(vscr) != TVSO(vr[32])); in tm_cvmx_set()
/linux/arch/powerpc/include/uapi/asm/
H A Delf.h115 # define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */
116 # define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */
125 # define ELF_NVRREG 33 /* includes vscr */
146 * The entry with index 32 contains the vscr as the last word (offset 12)
147 * within the quadword. This allows the vscr to be stored as either a
160 * vrsave along with vscr and so only uses 33 vectors for the register set
H A Dsigcontext.h46 * index 32 contains the vscr as the last word (offset 12) within the
47 * quadword. This allows the vscr to be stored as either a quadword (since
85 * registers and vscr/vrsave.
H A Dptrace.h149 * Get/set all the altivec registers v0..v31, vscr, vrsave, in one go.
151 * corresponding vector registers. Quadword 32 contains the vscr as the
H A Dkvm.h534 * VSCR register is documented as a 32-bit register in the ISA, but it can
535 * only be accesses via a vector register. Expose VSCR as a 32-bit register
/linux/arch/powerpc/kernel/
H A Dvector.S15 * Load state from memory into VMX registers including VSCR.
28 * Store VMX state into memory, including VSCR.
H A Dvecemu.c329 &current->thread.vr_state.vscr.u[3]); in emulate_altivec()
334 &current->thread.vr_state.vscr.u[3]); in emulate_altivec()
H A Dsignal_64.c141 /* Copy 33 vec registers (vr0..31 and vscr) to the stack */ in __unsafe_setup_sigcontext()
245 /* Copy 33 vec registers (vr0..31 and vscr) to the stack */ in setup_tm_sigcontexts()
393 /* Copy 33 vec registers (vr0..31 and vscr) from the stack */ in __unsafe_restore_sigcontext()
517 /* Copy 33 vec registers (vr0..31 and vscr) from the stack */ in restore_tm_sigcontexts()
H A Dsignal_32.c288 * use altivec. Since VSCR only contains 32 bits saved in the least in __unsafe_save_user_regs()
404 * use altivec. Since VSCR only contains 32 bits saved in the least in save_tm_user_regs_unsafe()
/linux/arch/powerpc/include/asm/
H A Dprocessor.h88 /* Complete AltiVec register set including VSCR */
91 vector128 vscr __attribute__((aligned(16))); member
/linux/tools/perf/pmu-events/arch/powerpc/power10/
H A Dpipeline.json285 … is held at dispatch while waiting on the Scoreboard. This event combines VSCR and FPSCR together."
475 …les dispatch is held while waiting on the Scoreboard. This event combines VSCR and FPSCR together."
/linux/tools/arch/powerpc/include/uapi/asm/
H A Dkvm.h534 * VSCR register is documented as a 32-bit register in the ISA, but it can
535 * only be accesses via a vector register. Expose VSCR as a 32-bit register
/linux/tools/testing/selftests/powerpc/pmu/ebb/
H A Debb_handler.S26 * VSCR | |
/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dmarked.json540 …ispatch held due to History Buffer full. Could be GPR/VSR/VMR/FPR/CR/XVF; CR; XVF (XER/VSCR/FPSCR)"
H A Dother.json1260 …lds because the History Buffer was full. Could be GPR/VSR/VMR/FPR/CR/XVF; CR; XVF (XER/VSCR/FPSCR)"
/linux/arch/powerpc/kvm/
H A Dbook3s_pr.c1609 *val = get_reg_val(id, vcpu->arch.vr_tm.vscr.u[3]); in kvmppc_get_one_reg_pr()
1708 vcpu->arch.vr.vscr.u[3] = set_reg_val(id, *val); in kvmppc_set_one_reg_pr()
/linux/arch/powerpc/platforms/powernv/
H A Didle.c884 * P10 loses CR, LR, CTR, FPSCR, VSCR, XER, TAR, SPRG2, and HSPRG1