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/linux/drivers/media/platform/amphion/
H A Dvpu_core.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2020-2021 NXP
21 #include "vpu.h"
29 void csr_writel(struct vpu_core *core, u32 reg, u32 val) in csr_writel() argument
31 writel(val, core->base + reg); in csr_writel()
34 u32 csr_readl(struct vpu_core *core, u32 reg) in csr_readl() argument
36 return readl(core->base + reg); in csr_readl()
39 static int vpu_core_load_firmware(struct vpu_core *core) in vpu_core_load_firmware() argument
44 if (!core->fw.virt) { in vpu_core_load_firmware()
45 dev_err(core->dev, "firmware buffer is not ready\n"); in vpu_core_load_firmware()
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H A Dvpu_imx8q.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2020-2021 NXP
15 #include "vpu.h"
42 int vpu_imx8q_setup_dec(struct vpu_dev *vpu) in vpu_imx8q_setup_dec() argument
46 vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_CLOCK_ENABLE_SET, 0x1f); in vpu_imx8q_setup_dec()
47 vpu_writel(vpu, offset + MFD_BLK_CTRL_MFD_SYS_RESET_SET, 0xffffffff); in vpu_imx8q_setup_dec()
52 int vpu_imx8q_setup_enc(struct vpu_dev *vpu) in vpu_imx8q_setup_enc() argument
57 int vpu_imx8q_setup(struct vpu_dev *vpu) in vpu_imx8q_setup() argument
61 vpu_readl(vpu, offset + 0x108); in vpu_imx8q_setup()
63 vpu_writel(vpu, offset + SCB_BLK_CTRL_SCB_CLK_ENABLE_SET, 0x1); in vpu_imx8q_setup()
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H A Dvpu.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2020-2021 NXP
9 #include <media/v4l2-device.h>
10 #include <media/v4l2-ctrls.h>
11 #include <media/v4l2-mem2mem.h>
18 #define VPU_INST_NULL_ID (-1L)
38 int (*setup)(struct vpu_dev *vpu);
39 int (*setup_encoder)(struct vpu_dev *vpu);
40 int (*setup_decoder)(struct vpu_dev *vpu);
41 int (*reset)(struct vpu_dev *vpu);
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H A Dvpu_dbg.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2020-2021 NXP
14 #include <media/v4l2-device.h>
16 #include "vpu.h"
62 struct vpu_inst *inst = s->private; in vpu_dbg_instance()
68 if (!inst->fh.m2m_ctx) in vpu_dbg_instance()
70 num = scnprintf(str, sizeof(str), "[%s]\n", vpu_core_type_desc(inst->type)); in vpu_dbg_instance()
74 num = scnprintf(str, sizeof(str), "tgig = %d,pid = %d\n", inst->tgid, inst->pid); in vpu_dbg_instance()
77 num = scnprintf(str, sizeof(str), "state = %s\n", vpu_codec_state_name(inst->state)); in vpu_dbg_instance()
82 inst->min_buffer_out, inst->min_buffer_cap); in vpu_dbg_instance()
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H A Dvpu_imx8q.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright 2020-2021 NXP
103 int vpu_imx8q_setup_dec(struct vpu_dev *vpu);
104 int vpu_imx8q_setup_enc(struct vpu_dev *vpu);
105 int vpu_imx8q_setup(struct vpu_dev *vpu);
106 int vpu_imx8q_reset(struct vpu_dev *vpu);
108 int vpu_imx8q_boot_core(struct vpu_core *core);
109 int vpu_imx8q_get_power_state(struct vpu_core *core);
110 int vpu_imx8q_on_firmware_loaded(struct vpu_core *core);
H A Dvpu_rpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2020-2021 NXP
15 #include "vpu.h"
21 int vpu_iface_check_memory_region(struct vpu_core *core, dma_addr_t addr, u32 size) in vpu_iface_check_memory_region() argument
23 struct vpu_iface_ops *ops = vpu_core_get_iface(core); in vpu_iface_check_memory_region()
25 if (!ops || !ops->check_memory_region) in vpu_iface_check_memory_region()
28 return ops->check_memory_region(core->fw.phys, addr, size); in vpu_iface_check_memory_region()
37 size = desc->end - desc->start; in vpu_rpc_check_buffer_space()
39 ptr1 = desc->wptr; in vpu_rpc_check_buffer_space()
40 ptr2 = desc->rptr; in vpu_rpc_check_buffer_space()
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H A Dvpu_v4l2.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2020-2021 NXP
14 #include <media/v4l2-device.h>
15 #include <media/v4l2-event.h>
16 #include <media/v4l2-mem2mem.h>
17 #include <media/v4l2-ioctl.h>
18 #include <media/videobuf2-v4l2.h>
19 #include <media/videobuf2-dma-contig.h>
20 #include <media/videobuf2-vmalloc.h>
21 #include "vpu.h"
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/linux/drivers/media/platform/mediatek/vcodec/decoder/
H A Dvdec_vpu_if.h1 /* SPDX-License-Identifier: GPL-2.0 */
13 * struct vdec_vpu_inst - VPU instance for video codec
15 * @core_id : core id used to separate different hardware
16 * @vsi : driver structure allocated by VPU side and shared to AP side
18 * @failure : VPU execution result status, 0: success, others: fail
19 * @inst_addr : VPU decoder instance address
23 * @signaled : 1 - Host has received ack message from VPU, 0 - not received
25 * @wq : wait queue to wait VPU message ack
49 * vpu_dec_init - init decoder instance and allocate required resource in VPU.
51 * @vpu: instance for vdec_vpu_inst
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H A Dvdec_vpu_if.c1 // SPDX-License-Identifier: GPL-2.0
14 struct vdec_vpu_inst *vpu = (struct vdec_vpu_inst *) in handle_init_ack_msg() local
15 (unsigned long)msg->ap_inst_addr; in handle_init_ack_msg()
17 mtk_vdec_debug(vpu->ctx, "+ ap_inst_addr = 0x%llx", msg->ap_inst_addr); in handle_init_ack_msg()
19 /* mapping VPU address to kernel virtual address */ in handle_init_ack_msg()
20 /* the content in vsi is initialized to 0 in VPU */ in handle_init_ack_msg()
21 vpu->vsi = mtk_vcodec_fw_map_dm_addr(vpu->ctx->dev->fw_handler, in handle_init_ack_msg()
22 msg->vpu_inst_addr); in handle_init_ack_msg()
23 vpu->inst_addr = msg->vpu_inst_addr; in handle_init_ack_msg()
25 mtk_vdec_debug(vpu->ctx, "- vpu_inst_addr = 0x%x", vpu->inst_addr); in handle_init_ack_msg()
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/linux/Documentation/devicetree/bindings/media/
H A Damphion,vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/amphion,vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Amphion VPU codec IP
11 - Ming Qian <ming.qian@nxp.com>
12 - Shijie Qin <shijie.qin@nxp.com>
14 description: |-
20 pattern: "^vpu@[0-9a-f]+$"
24 - enum:
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H A Drockchip-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/rockchip-vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Hantro G1 VPU codecs implemented on Rockchip SoCs
11 - Ezequiel Garcia <ezequiel@collabora.com>
19 - enum:
20 - rockchip,rk3036-vpu
21 - rockchip,rk3066-vpu
22 - rockchip,rk3288-vpu
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H A Dnxp,imx8mq-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Hantro G1/G2 VPU codecs implemented on i.MX8M SoCs
11 - Philipp Zabel <p.zabel@pengutronix.de>
19 - const: nxp,imx8mq-vpu
21 - const: nxp,imx8mq-vpu-g1
22 - const: nxp,imx8mq-vpu-g2
23 - const: nxp,imx8mm-vpu-g1
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H A Dcoda.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Chips&Media Coda multi-standard codec IP
10 - Philipp Zabel <p.zabel@pengutronix.de>
12 description: |-
14 called VPU (Video Processing Unit).
19 - items:
20 - const: fsl,imx27-vpu
21 - const: cnm,codadx6
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H A Dallwinner,sun50i-h6-vpu-g2.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/media/allwinner,sun50i-h6-vpu-g2.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Hantro G2 VPU codec implemented on Allwinner H6 SoC
11 - Jernej Skrabec <jernej.skrabec@gmail.com>
18 const: allwinner,sun50i-h6-vpu-g2
28 - description: Bus Clock
29 - description: Module Clock
31 clock-names:
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/linux/drivers/media/platform/verisilicon/
H A Dhantro_drv.c1 // SPDX-License-Identifier: GPL-2.0
3 * Hantro VPU codec driver
9 * Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
22 #include <media/v4l2-event.h>
23 #include <media/v4l2-mem2mem.h>
24 #include <media/videobuf2-core.h>
25 #include <media/videobuf2-vmalloc.h>
31 #define DRIVER_NAME "hantro-vpu"
36 "Debug level - higher value produces more verbose messages");
42 ctrl = v4l2_ctrl_find(&ctx->ctrl_handler, id); in hantro_get_ctrl()
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H A Dhantro.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Hantro VPU codec driver
8 * Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
21 #include <media/v4l2-ctrls.h>
22 #include <media/v4l2-device.h>
23 #include <media/v4l2-ioctl.h>
24 #include <media/v4l2-mem2mem.h>
25 #include <media/videobuf2-core.h>
26 #include <media/videobuf2-dma-contig.h>
45 * struct hantro_irq - irq handler and name
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/linux/arch/arm64/boot/dts/freescale/
H A Dimx8-ss-vpu.dtsi1 // SPDX-License-Identifier: GPL-2.0+
7 vpu: vpu@2c000000 { label
8 #address-cells = <1>;
9 #size-cells = <1>;
12 power-domains = <&pd IMX_SC_R_VPU>;
16 compatible = "fsl,imx6sx-mu";
19 #mbox-cells = <2>;
20 power-domains = <&pd IMX_SC_R_VPU_MU_0>;
25 compatible = "fsl,imx6sx-mu";
28 #mbox-cells = <2>;
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/linux/Documentation/devicetree/bindings/remoteproc/
H A Dingenic,vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/remoteproc/ingenic,vpu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 Inside the Video Processing Unit (VPU) of the recent JZ47xx SoCs from
11 Ingenic is a second Xburst MIPS CPU very similar to the main core.
16 - Paul Cercueil <paul@crapouillou.net>
20 const: ingenic,jz4770-vpu-rproc
24 - description: aux registers
25 - description: tcsm0 registers
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/linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_h264_req_multi_if.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <media/v4l2-h264.h>
10 #include <media/v4l2-mem2mem.h>
11 #include <media/videobuf2-dma-contig.h>
21 * enum vdec_h264_core_dec_err_type - core decode error type
32 * struct vdec_h264_slice_lat_dec_param - parameters for decode current frame
51 * struct vdec_h264_slice_info - decode information
74 * struct vdec_h264_slice_vsi - shared memory for decode information exchange
89 * dma address (AP-W, VPU-R)
90 * @dec: decode information (AP-R, VPU-W)
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H A Dvdec_hevc_req_multi_if.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <media/videobuf2-dma-contig.h>
24 { dst_param->cond = ((src_param->flags & (flag)) ? (1) : (0)); }
26 { dst_param->param = src_param->param; }
29 * enum vdec_hevc_core_dec_err_type - core decode error type
40 * struct mtk_hevc_dpb_info - hevc dpb information
55 * struct mtk_hevc_sps_param - parameters for sps
95 * struct mtk_hevc_pps_param - parameters for pps
138 * struct mtk_hevc_slice_header_param - parameters for slice header
177 * struct slice_api_hevc_scaling_matrix - parameters for scaling list
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/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
H A Dpipeline.json33 "PublicDescription": "No operation issued due to the frontend, pre-decode error",
36 "BriefDescription": "No operation issued due to the frontend, pre-decode error"
51 …he Vector Processing Unit (VPU). This event counts every cycle where there is a stall or an interl…
54 …he Vector Processing Unit (VPU). This event counts every cycle where there is a stall or an interl…
69 …e event counts for stalls that are caused by missing the cache or where the data is Non-cacheable",
72 …he event counts for stalls that are caused by missing the cache or where the data is Non-cacheable"
93 …due to the backend, VPU hazard. This event counts every cycle where the core stalls due to content…
96 …due to the backend, VPU hazard. This event counts every cycle where the core stalls due to content…
/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mq-vpu-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mq-vpu-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MQ VPU blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MQ VPU blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the VPU peripherals
15 located in the VPU domain of the SoC.
20 - const: fsl,imx8mq-vpu-blk-ctrl
[all …]
H A Dfsl,imx8mm-vpu-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mm-vpu-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MM VPU blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MM VPU blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the VPU peripherals
15 located in the VPU domain of the SoC.
20 - const: fsl,imx8mm-vpu-blk-ctrl
[all …]
/linux/drivers/media/platform/mediatek/mdp3/
H A Dmtk-mdp3-vpu.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
9 #include "mtk-mdp3-vpu.h"
10 #include "mtk-mdp3-core.h"
14 static inline struct mdp_dev *vpu_to_mdp(struct mdp_vpu_dev *vpu) in vpu_to_mdp() argument
16 return container_of(vpu, struct mdp_dev, vpu); in vpu_to_mdp()
19 static int mdp_vpu_shared_mem_alloc(struct mdp_vpu_dev *vpu) in mdp_vpu_shared_mem_alloc() argument
23 if (IS_ERR_OR_NULL(vpu)) in mdp_vpu_shared_mem_alloc()
26 dev = scp_get_device(vpu->scp); in mdp_vpu_shared_mem_alloc()
28 if (!vpu->param) { in mdp_vpu_shared_mem_alloc()
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/linux/Documentation/devicetree/bindings/display/
H A Damlogic,meson-vpu.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
17 DMC|---------------VPU (Video Processing Unit)----------------|------HHI------|
19 D |-------| |----| | | | | HDMI PLL |
20 D | vd2 | VIU | | Video Post | | Video Encoders |<---|-----VCLK |
21 R |-------| |----| Processing | | | | |
22 | osd2 | | | |---| Enci ----------|----|-----VDAC------|
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