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/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A Dvideo-pll.c30 static void dss_dpll_enable_scp_clk(struct dss_video_pll *vpll) in dss_dpll_enable_scp_clk() argument
32 REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */ in dss_dpll_enable_scp_clk()
35 static void dss_dpll_disable_scp_clk(struct dss_video_pll *vpll) in dss_dpll_disable_scp_clk() argument
37 REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */ in dss_dpll_disable_scp_clk()
40 static void dss_dpll_power_enable(struct dss_video_pll *vpll) in dss_dpll_power_enable() argument
42 REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */ in dss_dpll_power_enable()
51 static void dss_dpll_power_disable(struct dss_video_pll *vpll) in dss_dpll_power_disable() argument
53 REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */ in dss_dpll_power_disable()
58 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); in dss_video_pll_enable() local
67 dss_dpll_enable_scp_clk(vpll); in dss_video_pll_enable()
[all …]
/linux/drivers/gpu/drm/omapdrm/dss/
H A Dvideo-pll.c28 static void dss_dpll_enable_scp_clk(struct dss_video_pll *vpll) in dss_dpll_enable_scp_clk() argument
30 REG_MOD(vpll->clkctrl_base, 1, 14, 14); /* CIO_CLK_ICG */ in dss_dpll_enable_scp_clk()
33 static void dss_dpll_disable_scp_clk(struct dss_video_pll *vpll) in dss_dpll_disable_scp_clk() argument
35 REG_MOD(vpll->clkctrl_base, 0, 14, 14); /* CIO_CLK_ICG */ in dss_dpll_disable_scp_clk()
38 static void dss_dpll_power_enable(struct dss_video_pll *vpll) in dss_dpll_power_enable() argument
40 REG_MOD(vpll->clkctrl_base, 2, 31, 30); /* PLL_POWER_ON_ALL */ in dss_dpll_power_enable()
49 static void dss_dpll_power_disable(struct dss_video_pll *vpll) in dss_dpll_power_disable() argument
51 REG_MOD(vpll->clkctrl_base, 0, 31, 30); /* PLL_POWER_OFF */ in dss_dpll_power_disable()
56 struct dss_video_pll *vpll = container_of(pll, struct dss_video_pll, pll); in dss_video_pll_enable() local
65 dss_dpll_enable_scp_clk(vpll); in dss_video_pll_enable()
[all …]
/linux/drivers/mfd/
H A Dstw481x.c82 u8 vpll; in stw481x_startup() local
113 vpll = (ret >> 4) & 1; /* Save bit 4 */ in stw481x_startup()
118 vpll |= (ret >> 1) & 2; in stw481x_startup()
124 dev_info(&stw481x->client->dev, "VPLL: %u.%uV %s\n", in stw481x_startup()
125 vpll_val[vpll] / 100, vpll_val[vpll] % 100, in stw481x_startup()
/linux/Documentation/devicetree/bindings/display/bridge/
H A Dti,sn65dsi86.yaml40 vpll-supply:
153 - vpll-supply
179 vpll-supply = <&src_pp1800_s4a>;
244 vpll-supply = <&pm8916_l17>;
/linux/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip,dw-hdmi.yaml63 - vpll
67 - vpll
70 - vpll
/linux/Documentation/devicetree/bindings/mfd/
H A Dmc13xxx.txt95 vpll : regulator VPLL (register 32, bit 15)
/linux/drivers/clk/nuvoton/
H A Dclk-ma35d1.c88 { .fw_name = "vpll", },
334 { .fw_name = "vpll", },
347 { .fw_name = "vpll", },
510 hws[VPLL] = ma35d1_reg_clk_pll(dev, VPLL, pllmode[4], "vpll", in ma35d1_clocks_probe()
616 hws[DCUP_DIV] = ma35d1_clk_divider_table(dev, "dcup_div", "vpll", in ma35d1_clocks_probe()
H A Dclk-ma35d1-pll.c238 case VPLL: in ma35d1_clk_pll_recalc_rate()
270 case VPLL: in ma35d1_clk_pll_round_rate()
/linux/Documentation/devicetree/bindings/clock/
H A Dnuvoton,ma35d1-clk.yaml37 EPLL, and VPLL in sequential.
/linux/arch/arm/boot/dts/ti/omap/
H A Dmotorola-cpcap-mapphone.dtsi205 vpll: VPLL { label
/linux/arch/arm/boot/dts/
H A Dtps65910.dtsi55 regulator-compatible = "vpll";
/linux/arch/arm64/boot/dts/xilinx/
H A Dxlnx-zynqmp-clk.h16 #define VPLL 4 macro
/linux/arch/arm64/boot/dts/qcom/
H A Dsc7180-trogdor-ti-sn65dsi86.dtsi47 vpll-supply = <&pp1800_edp_vpll>;
/linux/include/dt-bindings/clock/
H A Dxlnx-zynqmp-clk.h23 #define VPLL 4 macro
H A Dnuvoton,ma35d1-clk.h24 #define VPLL 13 macro
/linux/Documentation/devicetree/bindings/display/panel/
H A Dsamsung,atna33xc20.yaml66 vpll-supply = <&src_pp1800_s4a>;
/linux/arch/arm64/boot/dts/nuvoton/
H A Dma35d1-iot-512m.dts45 <&clk VPLL>;
H A Dma35d1-som-256m.dts45 <&clk VPLL>;
/linux/drivers/video/fbdev/nvidia/
H A Dnv_type.h71 u32 vpll; member
/linux/drivers/regulator/
H A Dtps65910-regulator.c56 /* supported VPLL voltages in microvolts */
145 .name = "vpll",
283 EXT_CONTROL_REG_BITS(VPLL, 0, 6),
972 { .name = "vpll", .driver_data = (void *) &tps65910_regs[7] },
H A Dcpcap-regulator.c369 CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3,
445 CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3,
H A Dmc13892-regulator.c273 MC13892_DEFINE_REGU(VPLL, vpll, REGULATORMODE0, REGULATORSETTING0,
/linux/drivers/clk/rockchip/
H A Dclk-rk3576.c22 bpll, lpll, vpll, aupll, cpll, gpll, ppll, enumerator
297 PNAME(gpll_cpll_vpll_aupll_24m_p) = { "gpll", "cpll", "vpll", "aupll", "xin24m" };
301 PNAME(gpll_cpll_vpll_bpll_lpll_p) = { "gpll", "cpll", "vpll", "bpll_dummy", "lpll_dummy" };
305 PNAME(gpll_cpll_spll_vpll_bpll_lpll_p) = { "gpll", "cpll", "spll", "vpll", "bpll_dummy", "lpll_dumm…
306 PNAME(cpll_vpll_lpll_bpll_p) = { "cpll", "vpll", "lpll_dummy", "bpll_dummy" };
337 PNAME(dclk_ebc_p) = { "gpll", "cpll", "vpll", "aupll", "lpll_dummy",
371 [vpll] = PLL(pll_rk3588, PLL_VPLL, "vpll", mux_pll_p,
H A Dclk-rk3399.c19 lpll, bpll, dpll, cpll, gpll, npll, vpll, enumerator
152 PNAME(mux_pll_src_vpll_cpll_gpll_p) = { "vpll", "cpll", "gpll" };
153 PNAME(mux_pll_src_vpll_cpll_gpll_npll_p) = { "vpll", "cpll", "gpll",
155 PNAME(mux_pll_src_vpll_cpll_gpll_24m_p) = { "vpll", "cpll", "gpll",
231 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
697 GATE(0, "vpll_aclk_cci_src", "vpll", CLK_IGNORE_UNUSED,
/linux/drivers/gpu/drm/nouveau/dispnv04/
H A Dhw.c190 /* check whether vpll has been forced into single stage mode */ in nouveau_hw_get_pllvals()
254 /* the vpll on an unused head can come up with a random value, way in nouveau_hw_fix_bad_vpll()
276 NV_WARN(drm, "VPLL %d outwith limits, attempting to fix\n", head + 1); in nouveau_hw_fix_bad_vpll()

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