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Searched full:vivt (Results 1 – 9 of 9) sorted by relevance

/linux/arch/arm/include/asm/
H A Dhighmem.h25 * existing virtual mapping in an atomic context. With a VIVT cache this
H A Dmmu_context.h69 * cpu_switch_mm() needs to flush the VIVT caches. To avoid in check_and_switch_context()
H A Dcacheflush.h37 * effects are cache-type (VIVT/VIPT/PIPT) specific.
/linux/arch/arc/include/asm/
H A Dcacheflush.h46 #define flush_cache_dup_mm(mm) /* called on fork (VIVT only) */
/linux/arch/arm/mm/
H A Dflush.c246 * - VIVT cache: we need to also write back and invalidate all user in __flush_dcache_aliases()
323 * - VIVT: fully aliasing, so we need to handle every alias in our
H A Dmmap.c27 * in the VIVT case, we optimise out the alignment rules.
/linux/arch/arm/kernel/
H A Dsetup.c342 cache_is_vivt() ? "VIVT" : in cacheid_init()
345 cache_is_vivt() ? "VIVT" : in cacheid_init()
346 icache_is_vivt_asid_tagged() ? "VIVT ASID tagged" : in cacheid_init()
/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_meta.h277 * For non-VIVT SLCs the cacheability of the FW data in the SLC is selected in
/linux/arch/mips/mm/
H A Dc-r4k.c1343 c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT", in probe_pcache()