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/linux/drivers/clk/mediatek/
H A Dclk-mt8196-venc.c80 GATE_HWV_VEN10(CLK_VEN1_CKE0_LARB, "ven1_larb", "venc", 0),
81 GATE_HWV_VEN10(CLK_VEN1_CKE1_VENC, "ven1_venc", "venc", 4),
82 GATE_VEN10(CLK_VEN1_CKE2_JPGENC, "ven1_jpgenc", "venc", 8),
83 GATE_VEN10(CLK_VEN1_CKE3_JPGDEC, "ven1_jpgdec", "venc", 12),
84 GATE_VEN10(CLK_VEN1_CKE4_JPGDEC_C1, "ven1_jpgdec_c1", "venc", 16),
85 GATE_HWV_VEN10(CLK_VEN1_CKE5_GALS, "ven1_gals", "venc", 28),
87 "venc", 29),
89 "ven1_venc_xpc_ctrl", "venc", 30,
91 GATE_HWV_VEN10(CLK_VEN1_CKE6_GALS_SRAM, "ven1_gals_sram", "venc", 31),
93 GATE_HWV_VEN11(CLK_VEN1_RES_FLAT, "ven1_res_flat", "venc", 0),
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H A DMakefile23 obj-$(CONFIG_COMMON_CLK_MT6779_VENCSYS) += clk-mt6779-venc.o
36 obj-$(CONFIG_COMMON_CLK_MT6797_VENCSYS) += clk-mt6797-venc.o
53 obj-$(CONFIG_COMMON_CLK_MT2712_VENCSYS) += clk-mt2712-venc.o
99 obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
111 obj-$(CONFIG_COMMON_CLK_MT8186_VENCSYS) += clk-mt8186-venc.o
123 obj-$(CONFIG_COMMON_CLK_MT8188_VENCSYS) += clk-mt8188-venc.o
138 obj-$(CONFIG_COMMON_CLK_MT8192_VENCSYS) += clk-mt8192-venc.o
150 obj-$(CONFIG_COMMON_CLK_MT8195_VENCSYS) += clk-mt8195-venc.o
165 obj-$(CONFIG_COMMON_CLK_MT8196_VENCSYS) += clk-mt8196-venc.o
172 obj-$(CONFIG_COMMON_CLK_MT8365_VENC) += clk-mt8365-venc.o
H A Dclk-mt8365-venc.c24 /* VENC */
48 .name = "clk-mt8365-venc",
/linux/drivers/gpu/drm/meson/
H A Dmeson_encoder_hdmi.c81 /* For 420, pixel clock is half unlike venc clock */ in meson_encoder_hdmi_set_vclk()
101 /* VENC double pixels for 1080i, 720p and YUV420 modes */ in meson_encoder_hdmi_set_vclk()
112 "phy:%lluHz vclk=%lluHz venc=%lluHz hdmi=%lluHz enci=%d\n", in meson_encoder_hdmi_set_vclk()
114 priv->venc.hdmi_use_enci); in meson_encoder_hdmi_set_vclk()
117 venc_freq, hdmi_freq, priv->venc.hdmi_use_enci); in meson_encoder_hdmi_set_vclk()
157 /* For 420, pixel clock is half unlike venc clock */ in meson_encoder_hdmi_mode_valid()
173 /* VENC double pixels for 1080i, 720p and YUV420 modes */ in meson_encoder_hdmi_mode_valid()
186 "%s: vclk:%lluHz phy=%lluHz venc=%lluHz hdmi=%lluHz\n", in meson_encoder_hdmi_mode_valid()
229 /* VENC + VENC-DVI Mode setup */ in meson_encoder_hdmi_atomic_enable()
247 dev_dbg(priv->dev, "%s\n", priv->venc.hdmi_use_enci ? "VENCI" : "VENCP"); in meson_encoder_hdmi_atomic_enable()
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H A Dmeson_dw_hdmi.c64 * Pixel data arrives in 4:4:4 format from the VENC
69 * The VENC uses a DVI encoder on top of the ENCI
82 * - VENC & HDMI Clock setup for 480i to 1080p60
83 * - VENC Mode setup for 480i to 1080p60
285 /* For 420, pixel clock is half unlike venc clock */ in meson_hdmi_phy_setup_mode()
410 /* Temporary Disable VENC video stream */ in dw_hdmi_phy_init()
411 if (priv->venc.hdmi_use_enci) in dw_hdmi_phy_init()
422 /* Re-Enable VENC video stream */ in dw_hdmi_phy_init()
423 if (priv->venc.hdmi_use_enci) in dw_hdmi_phy_init()
433 if (priv->venc.hdmi_use_enci) in dw_hdmi_phy_init()
H A Dmeson_venc.c22 * VENC Handle the pixels encoding to the output formats.
34 * VENC paths :
39 * vd1---| |-| | | VENC /---------|----VDAC
935 /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */ in meson_venc_hdmi_venc_repeat()
1006 /* Repeat VENC pixels for 480/576i/p, 720p50/60 and 1080p50/60 */ in meson_venc_hdmi_mode_set()
1527 /* Invert polarity of HSYNC from VENC */ in meson_venc_hdmi_mode_set()
1531 /* Invert polarity of VSYNC from VENC */ in meson_venc_hdmi_mode_set()
1539 * Write rate to the async FIFO between VENC and HDMI. in meson_venc_hdmi_mode_set()
1546 * Read rate to the async FIFO between VENC and HDMI. in meson_venc_hdmi_mode_set()
1554 priv->venc.hdmi_repeat = hdmi_repeat; in meson_venc_hdmi_mode_set()
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H A Dmeson_dw_mipi_dsi.h63 * [18:16] RW in_color_mode: Define VENC data width. Default 0.
93 /* VENC data width */
/linux/Documentation/devicetree/bindings/display/ti/
H A Dti,omap4-dss.txt21 - DSS Submodules: RFBI, VENC, DSI, HDMI
59 VENC
63 - compatible: "ti,omap4-venc"
71 - Video port for VENC output
73 VENC Endpoint required properties:
H A Dti,omap2-dss.txt45 VENC
49 - compatible: "ti,omap2-venc"
54 VENC Endpoint required properties:
H A Dti,omap3-dss.txt56 VENC
60 - compatible: "ti,omap3-venc"
67 VENC Endpoint required properties:
/linux/Documentation/devicetree/bindings/power/
H A Damlogic,meson-ee-pwrc.yaml79 - const: venc
95 - const: venc
120 - const: venc
139 - const: venc
179 reset-names = "viu", "venc", "vcbus", "bt656",
/linux/drivers/media/platform/mediatek/vcodec/encoder/
H A Dmtk_vcodec_enc_pm.c37 dev_err(pm->dev, "[MTK VCODEC] Failed to get venc clock count"); in mtk_vcodec_init_enc_clk()
46 dev_err(pm->dev, "[MTK VCODEC] venc failed to get clk name %d", i); in mtk_vcodec_init_enc_clk()
52 dev_err(pm->dev, "[MTK VCODEC] venc devm_clk_get (%d)%s fail", i, in mtk_vcodec_init_enc_clk()
89 dev_err(pm->dev, "[MTK VCODEC] venc clk_prepare_enable %d %s fail %d", i, in mtk_vcodec_enc_clock_on()
H A DMakefile5 mtk-vcodec-enc-y := venc/venc_vp8_if.o \
6 venc/venc_h264_if.o \
H A Dvenc_vpu_if.c78 mtk_v4l2_venc_err(vpu->ctx, "venc msg id not correctly => 0x%x", msg->msg_id); in vpu_enc_ipi_handler()
143 vpu_enc_ipi_handler, "venc", in vpu_enc_init()
160 mtk_venc_err(vpu->ctx, "invalid venc vsi"); in vpu_enc_init()
/linux/Documentation/devicetree/bindings/media/
H A Dst,stm32mp25-video-codec.yaml7 title: STMicroelectronics STM32MP25 VDEC video decoder & VENC video encoder
15 and a VENC video hardware encoder peripheral based on Verisilicon
22 - st,stm32mp25-venc
/linux/drivers/video/fbdev/omap2/omapfb/dss/
H A DKconfig43 bool "VENC support"
103 bool "Sleep 20ms after VENC reset"
106 There is a 20ms sleep after VENC reset which seemed to fix the
H A DMakefile11 omapdss-$(CONFIG_FB_OMAP2_DSS_VENC) += venc.o
/linux/drivers/gpu/drm/omapdrm/
H A DKconfig55 bool "VENC support"
127 bool "Sleep 20ms after VENC reset"
130 There is a 20ms sleep after VENC reset which seemed to fix the
H A DMakefile25 omapdrm-$(CONFIG_OMAP2_DSS_VENC) += dss/venc.o
/linux/arch/arm/mach-omap2/
H A Domap_hwmod_2xxx_3xxx_ipblock_data.c37 * 'venc' class
42 .name = "venc",
/linux/Documentation/devicetree/bindings/display/
H A Damlogic,meson-vpu.yaml46 VENC: Video Encoders
49 The VENC is composed of the multiple pixel encoders
53 The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
/linux/drivers/media/platform/verisilicon/
H A Dstm32mp25_vpu_hw.c170 { "venc", stm32mp25_venc_irq },
174 "venc-clk"
/linux/Documentation/devicetree/bindings/soc/amlogic/
H A Damlogic,meson-gx-hhi-sysctrl.yaml146 reset-names = "viu", "venc", "vcbus", "bt656", "dvin",
198 reset-names = "viu", "venc", "vcbus", "vencl", "vid_lock";
/linux/drivers/media/platform/amphion/
H A DMakefile17 venc.o \
/linux/drivers/media/platform/qcom/venus/
H A DMakefile11 venus-enc-objs += venc.o venc_ctrls.o

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