| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | motorcomm,yt8xxx.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schema
[all...] |
| H A D | amlogic,meson-dwmac.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/net/amlogic,meson-dwmac.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Neil Armstrong <neil.armstrong@linaro.org>
12 - Martin Blumenstingl <martin.blumenstingl@googlemail.com>
20 - amlogic,meson6-dwmac
21 - amlogic,meson8b-dwmac
22 - amlogic,meson8m2-dwmac
23 - amlogic,meson-gxbb-dwmac
[all …]
|
| H A D | ti,dp83867.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - $ref: ethernet-controller.yaml#
14 - Andrew Davis <afd@ti.com>
18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
19 and 1000BASE-T Ethernet protocols.
34 nvmem-cells:
40 nvmem-cell-names:
42 - const: io_impedance_ctrl
[all …]
|
| H A D | fsl,fec.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Wei Fang <wei.fang@nxp.com>
12 - NXP Linux Team <linux-imx@nxp.com>
15 - $ref: ethernet-controller.yaml#
20 - enum:
21 - fsl,imx25-fec
22 - fsl,imx27-fec
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/iio/adc/ |
| H A D | st,stm32-dfsdm-adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/st,stm32-dfsdm-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
11 - Olivier Moysan <olivier.moysan@foss.st.com>
14 STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
17 - Sigma delta modulators (motor control, metering...)
18 - PDM microphones (audio digital microphone)
28 - st,stm32h7-dfsdm
[all …]
|
| H A D | ingenic,adc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2 # Copyright 2019-2020 Artur Rojek
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Artur Rojek <contact@artur-rojek.eu>
17 ADC clients must use the format described in
18 https://github.com/devicetree-org/dt-schema/blob/master/schemas/iio/iio-consumer.yaml,
19 giving a phandle and IIO specifier pair ("io-channels") to the ADC controller.
24 - ingenic,jz4725b-adc
25 - ingenic,jz4740-adc
[all …]
|
| H A D | adi,ad4130.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Cosmin Tanislav <cosmin.tanislav@analog.com>
15 https://www.analog.com/media/en/technical-documentation/data-sheets/AD4130-8.pdf
20 - adi,ad4130
27 description: phandle to the master clock (mclk)
29 clock-names:
31 - const: mclk
36 interrupt-names:
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/iio/imu/ |
| H A D | adi,adis16480.txt | 6 - compatible: Must be one of
12 * "adi,adis16495-1"
13 * "adi,adis16495-2"
14 * "adi,adis16495-3"
15 * "adi,adis16497-1"
16 * "adi,adis16497-2"
17 * "adi,adis16497-3"
18 - reg: SPI chip select number for the device
19 - spi-max-frequency: Max SPI frequency to use
20 see: Documentation/devicetree/bindings/spi/spi-bus.txt
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
|
| H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xus
[all...] |
| H A D | phy-rockchip-naneng-combphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,rk3568-naneng-combphy
16 - rockchip,rk3588-naneng-combphy
23 - description: reference clock
24 - description: apb clock
25 - description: pipe clock
[all …]
|
| H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
|
| H A D | phy-mtk-xsphy.txt | 1 MediaTek XS-PHY binding
2 --------------------------
4 The XS-PHY controller supports physical layer functionality for USB3.1
8 - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
9 soc-model is the name of SoC, such as mt3611 etc;
12 - "mediatek,mt3611-xsphy"
14 - #address-cells, #size-cells : should use the same values as the root node
15 - ranges: must be present
18 - reg : offset and length of register shared by multiple U3 ports,
20 shouldn't use the property.
[all …]
|
| H A D | nvidia,tegra194-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/sound/ |
| H A D | renesas,fsi.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas FIFO-buffered Serial Interface (FSI)
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
13 - $ref: dai-common.yaml#
22 - items:
23 - enum:
24 - renesas,fsi2-sh73a0 # SH-Mobile AG5
25 - renesas,fsi2-r8a7740 # R-Mobile A1
[all …]
|
| /freebsd/sys/contrib/alpine-hal/ |
| H A D | al_hal_serdes_25g_regs.h | 9 found at http://www.gnu.org/licenses/gpl-2.0.html
11 Alternatively, redistribution and use in source and binary forms, with or
29 LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
31 (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
132 /* Bit-wise write enable */
138 * 0x0 – Select reference clock from Bump
139 * 0x1 – Select inter-macro reference clock from the left side
141 * 0x3 – Select inter-macro reference clock from the right side
155 * 0x1 – Select reference clock from Bump
156 * 0x2 – Select inter-macro reference clock input from right side
[all …]
|
| /freebsd/share/man/man4/ |
| H A D | snd_hdspe.4 | 4 .\" Redistribution and use in source and binary forms, with or without
19 .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 .Bd -ragged -offset indent
42 .Bd -literal -offset indent
56 .Bl -bullet -compact
58 RME HDSPe AIO (optional AO4S-192 and AI4S-192 extension boards)
68 (32kHz-48kHz), 4 channels at double speed (64kHz-96kHz), and 2 channels at
69 quad speed (128kHz-192kHz).
77 .Bl -tag -width indent
[all …]
|
| H A D | snd_hdsp.4 | 5 .\" Redistribution and use in source and binary forms, with or without
20 .\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 .\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 .Bd -ragged -offset indent
43 .Bd -literal -offset indent
57 .Bl -bullet -compact
59 RME HDSP 9632 (optional AO4S-192 and AIS-192 extension boards)
69 (32kHz-48kHz) and 4 channels at double speed (64kHz-96kHz).
70 Only the HDSP 9632 can operate at quad speed (128kHz-192kHz), ADAT is
79 .Bl -tag -width indent
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/mfd/ |
| H A D | stericsson,ab8500.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson Analog Baseband AB8500 and AB8505
10 - Linus Walleij <linus.walleij@linaro.org>
13 the AB8500 "Analog Baseband" is the mixed-signals integrated circuit
14 handling power management (regulators), analog-to-digital conversion
15 (ADC), battery charging, fuel gauging of the battery, battery-backed
16 RTC, PWM, USB PHY and some GPIO lines in the ST-Ericsson U8500 platforms
21 USB charging handling has changed, and it has an embedded USB-to-serial
[all …]
|
| /freebsd/crypto/openssl/doc/designs/quic-design/ |
| H A D | congestion-control.md | 4 We use an abstract interface for the QUIC congestion controller to facilitate
5 use of pluggable QUIC congestion controllers in the future. The interface is
12 For details on the API, see the comments in `include/internal/quic_cc.h`.
19 `new` method, which provides access to a clock. While no current congestion
20 controller makes use of this facility, it can be used by future congestion
31 a clock. In the future it is likely that access at least to the statistics
33 interface has been avoided as this is currently an internal API for which no API
38 QUIC congestion control state is per-path, per-connection. Currently we support
47 manager's internal state directly, the interface between the two has been
50 manager in our implementation. See the comments in `include/internal/quic_cc.h`
[all …]
|
| /freebsd/sys/contrib/device-tree/src/riscv/starfive/ |
| H A D | jh7110-pine64-star64.dts | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 /dts-v1/;
7 #include "jh7110-common.dtsi"
18 starfive,tx-use-rgmii-clk;
19 assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
20 assigned-clock-parents = <&aoncrg JH7110_AONCLK_GMAC0_RMII_RTX>;
24 phy-handle = <&phy1>;
25 phy-mode = "rgmii-id";
26 starfive,tx-use-rgmii-clk;
27 assigned-clocks = <&syscrg JH7110_SYSCLK_GMAC1_TX>;
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/rtc/ |
| H A D | isil,isl1208.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Biju Das <biju.das.jz@bp.renesas.com>
11 - Trent Piepho <tpiepho@gmail.com>
20 - isil,isl1208
21 - isil,isl1209
22 - isil,isl1218
23 - isil,isl1219
31 clock-names:
[all …]
|
| H A D | rtc-ds1307.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/rtc/rtc-ds1307.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandre Belloni <alexandre.belloni@bootlin.com>
15 - enum:
16 - dallas,ds1307
17 - dallas,ds1308
18 - dallas,ds1337
19 - dallas,ds1338
[all …]
|
| H A D | rtc-ds1307.txt | 4 - compatible: should be one of:
23 - reg: I2C bus address of the device
26 - interrupts: rtc alarm interrupt.
27 - clock-output-names: From common clock binding to override the default output
28 clock name
29 - wakeup-source: Enables wake up of host system on alarm
30 - trickle-resistor-ohms : ds1339, ds1340 and ds 1388 only
34 - aux-voltage-chargeable: ds1339, ds1340, ds1388 and rx8130 only
40 - trickle-diode-disable : ds1339, ds1340 and ds1388 only
41 Do not use internal trickle charger diode
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | hi6220-clock.txt | 1 * Hisilicon Hi6220 Clock Controller
3 Clock control registers reside in different Hi6220 system controllers,
11 - compatible: the compatible should be one of the following strings to
12 indicate the clock controller functionality.
14 - "hisilicon,hi6220-acpu-sctrl"
15 - "hisilicon,hi6220-aoctrl"
16 - "hisilicon,hi6220-sysctrl"
17 - "hisilicon,hi6220-mediactrl"
18 - "hisilicon,hi6220-pmctrl"
19 - "hisilicon,hi6220-stub-clk"
[all …]
|