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Searched full:usb480m (Results 1 – 16 of 16) sorted by relevance

/linux/drivers/clk/rockchip/
H A Dclk-px30.c142 PNAME(mux_4plls_p) = { "gpll", "dummy_cpll", "usb480m", "npll" };
162 PNAME(mux_uart_src_p) = { "gpll", "xin24m", "usb480m", "npll" };
168 PNAME(mux_cif_out_p) = { "xin24m", "dummy_cpll", "npll", "usb480m" };
269 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
996 "usb480m",
H A Dclk-rv1108.c125 PNAME(mux_pll_src_4plls_p) = { "dpll", "gpll", "hdmiphy", "usb480m" };
130 PNAME(mux_mmc_src_p) = { "dpll", "gpll", "xin24m", "usb480m" };
131 PNAME(mux_pll_src_dpll_gpll_usb480m_p) = { "dpll", "gpll", "usb480m" };
147 PNAME(mux_dsp_src_p) = { "dpll", "gpll", "apll", "usb480m" };
194 MUX(0, "usb480m", mux_usb480m_pre_p, CLK_SET_RATE_PARENT,
H A Dclk-rk3328.c153 "usb480m" };
155 "usb480m" };
157 "xin24m", "usb480m" };
278 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
H A Dclk-rk3228.c141 PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "hdmiphy", "usb480m" };
146 PNAME(mux_mmc_src_p) = { "cpll", "gpll", "xin24m", "usb480m" };
147 PNAME(mux_pll_src_cpll_gpll_usb480m_p) = { "cpll", "gpll", "usb480m" };
253 MUX(0, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
H A Dclk-rv1126.c148 PNAME(mux_gpll_usb480m_cpll_xin24m_p) = { "gpll", "usb480m", "cpll", "xin24m" };
161 PNAME(mux_gpll_cpll_usb480m_xin24m_p) = { "gpll", "cpll", "usb480m", "xin24m" };
179 PNAME(mux_usb480m_gpll_p) = { "usb480m", "gpll" };
394 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
H A Dclk-rk3128.c137 PNAME(mux_pll_src_5plls_p) = { "cpll", "gpll", "gpll_div2", "gpll_div3", "usb480m" };
138 PNAME(mux_pll_src_4plls_p) = { "cpll", "gpll", "gpll_div2", "usb480m" };
231 MUX(SCLK_USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
H A Dclk-rk3036.c123 PNAME(mux_pll_src_apll_dpll_gpll_usb480m_p) = { "apll", "dpll", "gpll", "usb480m" };
428 MUX(SCLK_USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
H A Dclk-rk3308.c129 PNAME(mux_dpll_vpll0_vpll1_usb480m_xin24m_p) = { "dpll", "vpll0", "vpll1", "usb480m", "xin24m" };
284 MUX(USB480M, "usb480m", mux_usb480m_p, CLK_SET_RATE_PARENT,
/linux/include/dt-bindings/clock/
H A Drk3308-cru.h18 #define USB480M 14 macro
H A Drk3328-cru.h97 #define USB480M 123 macro
H A Dpx30-cru.h16 #define USB480M 14 macro
H A Drockchip,rv1126-cru.h72 #define USB480M 6 macro
H A Drk3568-cru.h80 #define USB480M 11 macro
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3308.dtsi201 assigned-clocks = <&cru USB480M>;
H A Drk3328.dtsi916 assigned-clocks = <&cru USB480M>;
H A Dpx30.dtsi875 assigned-clocks = <&cru USB480M>;