time\-slots (full) in projects: linux - OpenGrok search results

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/linux/tools/perf/pmu-events/arch/x86/pantherlake/
H A D	pipeline.json	25 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address… 50 …time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For th… 68 …nge from time to time due to power or thermal throttling. For this reason, this event may have a c… 84 …but has the same incrementing frequency as the time stamp counter. This event can approximate elap… 94 …ncy changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC)… 104 …but has the same incrementing frequency as the time stamp counter. This event can approximate elap… 121 …time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For th… 139 …nge from time to time due to power or thermal throttling. For this reason, this event may have a c… 153 "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event", 156 …"PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon eve… [all …]
/linux/Documentation/devicetree/bindings/net/
H A D	lantiq,pef2256.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Herve Codina <herve.codina@bootlin.com> 20 - const: lantiq,pef2256 27 - description: Master Clock 28 - description: System Clock Receive 29 - description: System Clock Transmit 31 clock-names: 33 - const: mclk [all …]`
/linux/tools/perf/pmu-events/arch/x86/alderlaken/
H A D	adln-metrics.json	4 "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC", 11 "MetricExpr": "cstate_core@c1\\-residency@ / TSC", 18 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", 25 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", 32 "MetricExpr": "cstate_core@c6\\-residency@ / TSC", 39 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", 46 "MetricExpr": "cstate_core@c7\\-residency@ / TSC", 53 "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC", 60 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", 74 …"BriefDescription": "Counts the number of issue slots that were not consumed by the backend due to… [all …]
H A D	pipeline.json	191 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address… 282 …e core frequency may change from time to time. For this reason this event may have a changing rati… 291 …e core frequency may change from time to time. For this reason this event may have a changing rati… 307 …ncy changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC)… 316 …ncy changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC)… 324 …e core frequency may change from time to time. For this reason this event may have a changing rati… 333 …e core frequency may change from time to time. For this reason this event may have a changing rati… 394 …ounts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stor… 428 …"BriefDescription": "Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no u… 436 …Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scorebo… [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a75/
H A D	pipeline.json	21 "PublicDescription": "Duration for which all slots in the Load-Store Unit (LSU) are busy", 24 "BriefDescription": "Duration for which all slots in the Load-Store Unit (LSU) are busy" 27 …for which all slots in the load-store issue queue are busy. This event counts the cycles where all… 30 …for which all slots in the load-store issue queue are busy. This event counts the cycles where all… 33 …ch all slots in the data processing issue queue are busy. This event counts the cycles where all s… 36 …ch all slots in the data processing issue queue are busy. This event counts the cycles where all s… 39 …cDescription": "Duration for which all slots in the data engine issue queue are busy. This event i… 42 …fDescription": "Duration for which all slots in the data engine issue queue are busy. This event i…
/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A D	pipeline.json	97 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address… 162 …e core frequency may change from time to time. For this reason this event may have a changing rati… 171 …e core frequency may change from time to time. For this reason this event may have a changing rati… 179 …ncy changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC)… 187 …ncy changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC)… 196 …ncy changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC)… 291 …ounts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stor… 307 …"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend … 311 …slots that were not consumed by the backend because allocation is stalled due to a mispredicted ju… 316 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… [all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A D	pipeline.json	97 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address… 162 …e core frequency may change from time to time. For this reason this event may have a changing rati… 171 …e core frequency may change from time to time. For this reason this event may have a changing rati… 179 …ncy changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC)… 187 …ncy changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC)… 196 …ncy changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC)… 291 …ounts the number of machine clears due to a page fault. Counts both I-Side and D-Side (Loads/Stor… 307 …"BriefDescription": "Counts the total number of issue slots that were not consumed by the backend … 311 …slots that were not consumed by the backend because allocation is stalled due to a mispredicted ju… 316 …"BriefDescription": "Counts the number of issue slots every cycle that were not consumed by the ba… [all …]
/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A D	grr-metrics.json	4 "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC", 11 "MetricExpr": "cstate_core@c1\\-residency@ / TSC", 18 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", 25 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", 32 "MetricExpr": "cstate_core@c6\\-residency@ / TSC", 39 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", 46 "MetricExpr": "cstate_core@c7\\-residency@ / TSC", 53 "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC", 59 …"BriefDescription": "Cycles per instruction retired; indicating how much time each executed instru… 71 "BriefDescription": "Percentage of time spent in the active CPU power state C0", [all …]
/linux/tools/perf/Documentation/
H A D	topdown.txt	2 --------------------- 11 perf stat --topdown implements this using available metrics that vary 14 % perf stat -a --topdown -I1000 15 # time % tma_retiring % tma_backend_bound % tma_frontend_bound % tma_bad_specula… 38 On Ice Lake, there is a new fixed counter 3: SLOTS, which reports 39 "pipeline SLOTS" (cycles multiplied by core issue width) and a 40 metric register that reports slots ratios for the different bottleneck 52 The application opens a group with fixed counter 3 (SLOTS) and any 76 /* Open slots counter file descriptor for current task. */ 77 struct perf_event_attr slots = { [all …]
/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A D	srf-metrics.json	4 "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC", 11 "MetricExpr": "cstate_core@c1\\-residency@ / TSC", 18 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", 25 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", 32 "MetricExpr": "cstate_core@c6\\-residency@ / TSC", 39 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", 46 "MetricExpr": "cstate_core@c7\\-residency@ / TSC", 53 "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC", 59 …"BriefDescription": "Cycles per instruction retired; indicating how much time each executed instru… 83 "BriefDescription": "Percentage of time spent in the active CPU power state C0", [all …]
H A D	frontend.json	19 …ired that are tagged after a branch instruction causes bubbles/empty issue slots due to a baclear", 27 …red that are tagged after a branch instruction causes bubbles /empty issue slots due to a btclear", 52 …s the number of instructions retired that were tagged because empty issue slots were seen before t… 60 …s the number of instructions retired that were tagged because empty issue slots were seen before t… 76 …red that are tagged after a branch instruction causes bubbles/empty issue slots due to a predecode… 84 …"BriefDescription": "Counts every time the code stream enters into a new cache line by walking seq… 92 …time the code stream enters into a new cache line by walking sequential from the previous line or … 100 "BriefDescription": "Counts the number of cycles that the micro-sequencer is busy.",
/linux/fs/btrfs/
H A D	inode-item.c	`1 // SPDX-License-Identifier: GPL-2.0 9 #include "inode-item.h" 10 #include "disk-io.h" 12 #include "space-info.h" 14 #include "extent-tree.h" 15 #include "file-item.h" 35 if (len != name->len) in btrfs_find_name_in_backref() 37 if (memcmp_extent_buffer(leaf, name->name, name_ptr, in btrfs_find_name_in_backref() 38 name->len) == 0) in btrfs_find_name_in_backref() 60 * looking through any collisions so most of the time this is in btrfs_find_name_in_ext_backref() [all …]`
/linux/Documentation/filesystems/
H A D	vfat.rst	`10 mount -t vfat /dev/fd0 /mnt 42 -20: If current process is in group of file's group ID, 45 -2: Other users can change timestamp. 69 There is also an option of doing UTF-8 translations 76 UTF-8 is the filesystem safe version of Unicode that 79 If 'uni_xlate' gets set, UTF-8 gets disabled. 141 Interpret timestamps as UTC rather than local time. 143 between local time (as used by Windows on FAT) and UTC 147 local time. 150 Set offset for conversion of timestamps from local time [all …]`
/linux/tools/perf/pmu-events/arch/x86/alderlake/
H A D	pipeline.json	30 …xecuting divide or square root operations. Accounts for integer and floating-point operations. Ava… 370 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address… 403 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", 441 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)", 445 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re… 523 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that… 548 …Description": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more… 552 …tion": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more… 558 …Description": "Core clocks when the thread is in the C0.2 light-weight faster wakeup time but less… 562 …tion": "Counts core clocks when the thread is in the C0.2 light-weight faster wakeup time but less… [all …]
H A D	adl-metrics.json	4 "MetricExpr": "cstate_pkg@c10\\-residency@ / TSC", 11 "MetricExpr": "cstate_core@c1\\-residency@ / TSC", 18 "MetricExpr": "cstate_pkg@c2\\-residency@ / TSC", 25 "MetricExpr": "cstate_pkg@c3\\-residency@ / TSC", 32 "MetricExpr": "cstate_core@c6\\-residency@ / TSC", 39 "MetricExpr": "cstate_pkg@c6\\-residency@ / TSC", 46 "MetricExpr": "cstate_core@c7\\-residency@ / TSC", 53 "MetricExpr": "cstate_pkg@c8\\-residency@ / TSC", 60 "MetricExpr": "((msr@aperf@ - cycles) / msr@aperf@ if msr@smi@ > 0 else 0)", 75 "MetricExpr": "(max(cycles\\-t - cycles\\-ct, 0) / cycles if has_event(cycles\\-t) else 0)", [all …]
/linux/tools/perf/pmu-events/arch/x86/arrowlake/
H A D	pipeline.json	18 …y executing divide or square root operations. Accounts for integer and floating-point operations.", 366 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address… 384 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address… 437 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", 447 …"BriefDescription": "Mispredicted non-taken conditional branch instructions retired. This precise … 451 …"PublicDescription": "Mispredicted non-taken conditional branch instructions retired. This precise… 543 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)", 547 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re… 652 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that… 686 …Description": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more… [all …]
H A D	frontend.json	17 …s the front-end is resteered when it finds a branch instruction in a fetch line. This is called Un… 37 …e number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length … 52 "BriefDescription": "DSB-to-MITE switch true penalty cycles.", 56 …"PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previou… 96 …ions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Availabl… 102 …ired that are tagged after a branch instruction causes bubbles/empty issue slots due to a baclear", 111 …ired that are tagged after a branch instruction causes bubbles/empty issue slots due to a baclear", 120 …red that are tagged after a branch instruction causes bubbles /empty issue slots due to a btclear", 129 …red that are tagged after a branch instruction causes bubbles /empty issue slots due to a btclear", 182 …ode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to … [all …]
/linux/tools/perf/pmu-events/arch/x86/goldmontplus/
H A D	pipeline.json	164 …e core frequency may change from time to time. For this reason this event may have a changing rati… 189 …nge from time. This event is not affected by core frequency changes but counts as if the core is … 225 …S records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.", 229 "BriefDescription": "Instructions retired - using Reduced Skid PEBS feature", 238 "BriefDescription": "Unfilled issue slots per cycle", 242 …"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by th… 246 "BriefDescription": "Unfilled issue slots per cycle to recover", 250 …slots per core cycle that were not consumed by the backend because allocation is stalled waiting f… 255 … "BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend", 259 …ssue slots per core cycle that were not consumed because of a full resource in the backend. Inclu… [all …]
/linux/tools/perf/pmu-events/arch/x86/goldmont/
H A D	pipeline.json	164 …e core frequency may change from time to time. For this reason this event may have a changing rati… 189 …nge from time. This event is not affected by core frequency changes but counts as if the core is … 224 …S records can be collected only on IA32_PMC0, only one event can use the PEBS facility at a time.", 228 "BriefDescription": "Unfilled issue slots per cycle", 232 …"PublicDescription": "Counts the number of issue slots per core cycle that were not consumed by th… 236 "BriefDescription": "Unfilled issue slots per cycle to recover", 240 …slots per core cycle that were not consumed by the backend because allocation is stalled waiting f… 245 … "BriefDescription": "Unfilled issue slots per cycle because of a full resource in the backend", 249 …ssue slots per core cycle that were not consumed because of a full resource in the backend. Inclu… 279 …, but did not occur because the store data was not available at the right time. The forward might… [all …]
/linux/tools/perf/pmu-events/arch/x86/lunarlake/
H A D	pipeline.json	18 …y executing divide or square root operations. Accounts for integer and floating-point operations.", 321 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address… 383 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", 393 …"BriefDescription": "Mispredicted non-taken conditional branch instructions retired. This precise … 397 …"PublicDescription": "Mispredicted non-taken conditional branch instructions retired. This precise… 480 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)", 484 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re… 571 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that… 605 …Description": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more… 609 …tion": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more… [all …]
/linux/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A D	fsl,cpm1-scc-qmc.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Herve Codina <herve.codina@bootlin.com> 19 - enum: 20 - fsl,mpc885-scc-qmc 21 - fsl,mpc866-scc-qmc 22 - const: fsl,cpm1-scc-qmc 26 - description: SCC (Serial communication controller) register base [all …]`
H A D	fsl,qe-ucc-qmc.yaml	`1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/soc/fsl/cpm_qe/fsl,qe-ucc-qmc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Herve Codina <herve.codina@bootlin.com> 19 - enum: 20 - fsl,mpc8321-ucc-qmc 21 - const: fsl,qe-ucc-qmc 25 - description: UCC (Unified communication controller) register base 26 - description: Dual port ram base [all …]`
/linux/tools/perf/pmu-events/arch/x86/meteorlake/
H A D	pipeline.json	18 …xecuting divide or square root operations. Accounts for integer and floating-point operations. Ava… 256 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address… 309 "BriefDescription": "Mispredicted non-taken conditional branch instructions retired.", 319 …"BriefDescription": "Mispredicted non-taken conditional branch instructions retired. This precise … 323 …"PublicDescription": "Mispredicted non-taken conditional branch instructions retired. This precise… 367 …"BriefDescription": "Miss-predicted near indirect branch instructions retired (excluding returns)", 371 …"PublicDescription": "Counts miss-predicted near indirect branch instructions retired excluding re… 458 …"PublicDescription": "This is a non-precise version (that is, does not use PEBS) of the event that… 483 …Description": "Core clocks when the thread is in the C0.1 light-weight slower wakeup time but more… 487 …tion": "Counts core clocks when the thread is in the C0.1 light-weight slower wakeup time but more… [all …]
/linux/drivers/firmware/efi/libstub/
H A D	randomalloc.c	1 // SPDX-License-Identifier: GPL-2.0 13 * Return the number of slots covered by this entry, i.e., the number of 25 if (md->type != EFI_CONVENTIONAL_MEMORY) in get_entry_num_slots() 28 if (md->attribute & EFI_MEMORY_HOT_PLUGGABLE) in get_entry_num_slots() 32 (md->attribute & EFI_MEMORY_SP)) in get_entry_num_slots() 35 region_end = min(md->phys_addr + md->num_pages * EFI_PAGE_SIZE - 1, in get_entry_num_slots() 40 first_slot = round_up(max(md->phys_addr, alloc_min), align); in get_entry_num_slots() 41 last_slot = round_down(region_end - size + 1, align); in get_entry_num_slots() 46 return ((unsigned long)(last_slot - first_slot) >> align_shift) + 1; in get_entry_num_slots() 55 #define MD_NUM_SLOTS(md) ((md)->virt_addr) [all …]
/linux/drivers/gpu/drm/xe/
H A D	xe_bo_doc.h	`1 /* SPDX-License-Identifier: MIT / 25 ---------- 38 * -------- 44 * the backing store can be deferred from creation time until first use which is 53 * the BO dma-resv slots / lock point to the VM's dma-resv slots / lock (all 54 * private BOs to a VM share common dma-resv slots / lock). 62 * own unique dma-resv slots / lock. An external BO will be in an array of all 90 * ---------------- 109 * dma-resv slots. 118 * ------------------------------ [all …]`

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