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/linux/Documentation/userspace-api/media/v4l/
H A Dmetafmt-pisp-be.rst18 The PiSP Back End processes images in tiles, and its configuration requires
31 to be processed and is therefore shared across all the tiles of the image. So
33 across all tiles from the same frame.
41 As the ISP processes images in tiles, each set of tiles parameters describe how
43 parameters consist of 160 bytes of data and to process a batch of tiles several
44 sets of tiles parameters are required.
46 Tiles parameters are passed to the ISP by populating the member of
H A Dpixfmt-yuv-planar.rst103 - 64x32 tiles
112 - 16x16 tiles
126 - 4x4 tiles
154 - 4x4 tiles
161 - 16x32 / 16x16 tiles tiled low bits
168 - 16x32 / 16x16 tiles raster low bits
390 pixels in 2D 16x16 tiles, and stores tiles linearly in memory.
395 pixels in 2D 64x32 tiles, and stores 2x2 groups of tiles in
399 If the vertical resolution is an odd number of tiles, the last row of
400 tiles is stored in linear order. The layouts of the luma and chroma
[all …]
/linux/Documentation/devicetree/bindings/arm/
H A Darm,integrator.yaml14 They are ARMv4, ARMv5 and ARMv6-capable using different core tiles,
15 so the system is modular and can host a variety of CPU tiles called
16 "core tiles" and referred to in the device tree as "core modules".
/linux/drivers/gpu/drm/imagination/
H A Dpvr_rogue_cr_defs_client.h103 * must be configured in terms of the number of tiles in X & Y axis.
123 * as the number of tiles defined in the RGX_CR_TE_SCREEN register.
143 * Macrotile width, in tiles. A value of zero corresponds to the maximum size
150 * Macrotile height, in tiles. A value of zero corresponds to the maximum size
/linux/drivers/gpu/drm/xe/
H A Dxe_tile_types.h34 * at the root tile, and the MSTR_TILE_INTR register will report which tiles
72 * still be accessed by all tiles' GTs.
80 * still be accessed by all tiles' GTs.
H A Dxe_tile_sysfs_types.h17 * When dealing with multiple TILEs, this struct helps to understand which
/linux/Documentation/admin-guide/perf/
H A Dthunderx2-pmu.rst9 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
11 to the total number of channels/tiles.
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
H A Dnv25.c33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv25_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv25_fb_tile_comp()
H A Dnv35.c33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv35_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv35_fb_tile_comp()
H A Dnv36.c33 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv36_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv36_fb_tile_comp()
H A Dnv40.c33 u32 tiles = DIV_ROUND_UP(size, 0x80); in nv40_fb_tile_comp() local
34 u32 tags = round_up(tiles / fb->ram->parts, 0x100); in nv40_fb_tile_comp()
H A Dnv20.c46 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv20_fb_tile_comp() local
47 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv20_fb_tile_comp()
H A Dnv30.c52 u32 tiles = DIV_ROUND_UP(size, 0x40); in nv30_fb_tile_comp() local
53 u32 tags = round_up(tiles / fb->ram->parts, 0x40); in nv30_fb_tile_comp()
/linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_vp9_req_lat_if.c275 struct vdec_vp9_slice_tiles tiles; member
887 struct vdec_vp9_slice_tiles *tiles; in vdec_vp9_slice_setup_tile() local
897 tiles = &vsi->frame.tiles; in vdec_vp9_slice_setup_tile()
898 tiles->actual_rows = 0; in vdec_vp9_slice_setup_tile()
911 tiles->mi_rows[i] = (offset + 7) >> 3; in vdec_vp9_slice_setup_tile()
912 if (tiles->mi_rows[i]) in vdec_vp9_slice_setup_tile()
913 tiles->actual_rows++; in vdec_vp9_slice_setup_tile()
920 tiles->mi_cols[i] = (offset + 7) >> 3; in vdec_vp9_slice_setup_tile()
1058 * parse tiles according to `6.4 Decode tiles syntax`
1061 * frame contains uncompress header, compressed header and several tiles.
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/linux/drivers/gpu/ipu-v3/
H A Dipu-image-convert.c27 * of 4*4 or 16 tiles. A conversion is then carried out for each
34 * of tiles as the output frame:
62 * output image. Tiles are numbered row major from top left to bottom
347 "task %u: ctx %p: %s format: %dx%d (%dx%d tiles), %c%c%c%c\n", in dump_format()
389 * Calculate downsizing coefficients, which are the same for all tiles,
392 * Also determine the number of tiles necessary to guarantee that no tile
448 "%s: hscale: >>%u, *8192/%u vscale: >>%u, *8192/%u, %ux%u tiles\n", in calc_image_resize_coefficients()
526 * Output tiles must start at a multiple of 8 bytes horizontally and in find_best_seam()
538 * Tiles in the right row / bottom column may not be allowed to in find_best_seam()
647 * Fill in left position and width and for all tiles in an input column, and
[all …]
/linux/arch/arm/include/debug/
H A Dvexpress.S28 @ - all other (RS1 complaint) tiles use UART mapped
/linux/Documentation/devicetree/bindings/media/
H A Draspberrypi,pispbe.yaml16 in tiles and produces images consumable by applications.
/linux/arch/riscv/
H A DKconfig.socs76 The Blackhole SoC contains four RISC-V CPU tiles each
/linux/Documentation/ABI/testing/
H A Dsysfs-driver-hid-picolcd41 tiles get changed and it's not appropriate to expect the application
/linux/drivers/video/fbdev/
H A Dgbefb.c689 The GBE hardware uses a tiled memory to screen mapping. Tiles are in gbefb_set_par()
692 tiles on the right and/or bottom of the screen if needed. in gbefb_set_par()
710 Tiles have the advantage that they can be allocated individually in in gbefb_set_par()
716 Tiles are still allocated as independent chunks of 64KB of in gbefb_set_par()
751 /* Tell gbe about the tiles table location */ in gbefb_set_par()
1159 printk(KERN_ERR "gbefb: couldn't allocate tiles table\n"); in gbefb_probe()
1193 /* map framebuffer memory into tiles table */ in gbefb_probe()
/linux/drivers/media/platform/verisilicon/
H A Dhantro_hevc.c90 /* Need to reallocate due to tiles passed via PPS */ in tile_buffer_reallocate()
260 * Maximum number of tiles times width and height (2 bytes each), in hantro_hevc_dec_init()
/linux/Documentation/devicetree/bindings/clock/
H A Darm,syscon-icst.yaml30 In the core modules and logic tiles, the ICST is a configurable clock fed
/linux/include/uapi/drm/
H A Dvc4_drm.h166 /* By default, the kernel gets to choose the order that the tiles are
167 * rendered in. If this is set, then the tiles will be rendered in a
/linux/Documentation/gpu/
H A Ddrm-vm-bind-async.rst209 * @tile_mask: Mask for which tiles to create binds for, 0 == All tiles,
/linux/drivers/hid/
H A Dhid-picolcd_fb.c21 * This display area is tiled over 4 controllers with 8 tiles
224 /* Update fb_vbitmap from the screen_buffer and send changed tiles to device */
242 * Do this one tile after the other and push those tiles that changed. in picolcd_fb_update()

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