Home
last modified time | relevance | path

Searched +full:system +full:- +full:reboot +full:- +full:controller (Results 1 – 25 of 118) sorted by relevance

12345

/linux/Documentation/devicetree/bindings/arm/hisilicon/controller/
H A Dsysctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/hisilicon/controller/sysctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Hisilicon system controller
10 - Wei Xu <xuwei5@hisilicon.com>
13 The Hisilicon system controller is used on many Hisilicon boards, it can be
14 used to assist the slave core startup, reboot the system, etc.
16 There are some variants of the Hisilicon system controller, such as HiP01,
17 Hi3519, Hi6220 system controller, each of them is mostly compatible with the
[all …]
/linux/Documentation/devicetree/bindings/power/reset/
H A Dapple,smc-reboot.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/power/reset/apple,smc-reboot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple SMC Reboot Controller
10 The Apple System Management Controller (SMC) provides reboot functionality
12 system state information related to boot, shutdown, and panic events.
15 - Sven Peter <sven@kernel.org>
19 const: apple,smc-reboot
21 nvmem-cells:
[all …]
H A Dsyscon-reboot.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/power/reset/syscon-reboot.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sebastian Reichel <sre@kernel.org>
16 mask defined in the reboot node. Default will be little endian mode, 32 bit
18 parental dt-node. So the SYSCON reboot node should be represented as a
19 sub-node of a "syscon", "simple-mfd" node. Though the regmap property
20 pointing to the system controller node is also supported.
25 - syscon-reboot
[all …]
/linux/Documentation/devicetree/bindings/arm/bcm/
H A Dbrcm,brcmstb.txt2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
11 #address-cells = <2>;
12 #size-cells = <2>;
16 Further, syscon nodes that map platform-specific registers used for general
17 system control is required:
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-cpu-biu-ctrl",
21 "brcm,brcmstb-cpu-biu-ctrl",
[all …]
H A Dbrcm,bcm63138.txt1 Broadcom BCM63138 DSL System-on-a-Chip device tree bindings
2 -----------------------------------------------------------
4 Boards compatible with the BCM63138 DSL System-on-a-Chip should have the
12 initialization as well as a 'resets' phandle to the correct PMB controller as
13 defined in reset/brcm,bcm63138-pmb.txt for this secondary CPU, and an
14 'enable-method' property.
17 - compatible: should be "brcm,bcm63138-bootlut"
18 - reg: register base address and length for the Boot Lookup table
21 - enable-method: should be "brcm,bcm63138"
24 - enable-method: should be "brcm,bcm63138"
[all …]
/linux/Documentation/devicetree/bindings/mfd/
H A Dti,nspire-misc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2022-2023 Texas Instruments Incorporated - https://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mfd/ti,nspire-misc.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Andrew Davis <afd@ti.com>
14 System controller node represents a register region containing a set
17 controller.
22 - enum:
23 - ti,nspire-misc
[all …]
/linux/arch/powerpc/boot/dts/
H A Dturris1x.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2013 - 2022 CZ.NIC z.s.p.o. (http://www.nic.cz/)
8 * and available at: https://docs.turris.cz/hw/turris-1x/turris-1x/
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/leds/common.h>
14 /include/ "fsl/p2020si-pre.dtsi"
40 /* PCA9557PW GPIO controller for boot config */
41 gpio-controller@18 {
45 #gpio-cells = <2>;
[all …]
/linux/Documentation/devicetree/bindings/soc/samsung/
H A Dexynos-pmu.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/soc/samsung/exynos-pmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
18 - google,gs101-pmu
19 - samsung,exynos3250-pmu
20 - samsung,exynos4210-pmu
21 - samsung,exynos4212-pmu
22 - samsung,exynos4412-pmu
[all …]
/linux/arch/mips/boot/dts/mti/
H A Dmalta.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/mips-gic.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
16 cpu_intc: interrupt-controller {
17 compatible = "mti,cpu-interrupt-controller";
19 interrupt-controller;
20 #interrupt-cells = <1>;
[all …]
H A Dsead3.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "mti,sead-3";
14 model = "MIPS SEAD-3";
17 stdout-path = "serial1:115200";
36 cpu_intc: interrupt-controller {
37 compatible = "mti,cpu-interrupt-controller";
[all …]
/linux/arch/mips/boot/dts/img/
H A Dboston.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/boston-clock.h>
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/mips-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
15 stdout-path = "uart0:115200";
23 #address-cells = <1>;
[all …]
/linux/Documentation/devicetree/bindings/mips/lantiq/
H A Drcu.txt4 This binding describes the RCU (reset controller unit) multifunction device,
5 where each sub-device has its own set of registers.
14 -------------------------------------------------------------------------------
16 - compatible : The first and second values must be:
17 "lantiq,xrx200-rcu", "simple-mfd", "syscon"
18 - reg : The address and length of the system control registers
21 -------------------------------------------------------------------------------
24 compatible = "lantiq,xrx200-rcu", "simple-mfd", "syscon";
27 big-endian;
29 reset0: reset-controller@10 {
[all …]
/linux/arch/arm/mach-mvebu/
H A Dsystem-controller.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * System controller support for Armada 370, 375 and XP platforms.
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * but rather provide system-level features. This basic
14 * system-controller driver provides a device tree binding for those
19 * soft-reset, but it might be extended in the future.
26 #include <linux/reboot.h>
28 #include "mvebu-soc-id.h"
79 .compatible = "marvell,orion-system-controller",
[all …]
/linux/Documentation/devicetree/bindings/timer/
H A Dvia,vt8500-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/via,vt8500-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 This is the timer block that is a standalone part of the system power
11 management controller on VIA/WonderMedia SoCs (VIA VT8500 and alike).
12 The hardware has a single 32-bit counter running at 3 MHz and four match
14 and the first of which can also serve as the system watchdog (if the
15 watchdog function is enabled, it will reset the system upon match instead
19 - Alexey Charkov <alchark@gmail.com>
[all …]
/linux/arch/arm64/boot/dts/exynos/google/
H A Dgs101-pixel-common.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree nodes common for all GS101-based Pixel
5 * Copyright 2021-2023 Google LLC
6 * Copyright 2023 Linaro Ltd - <peter.griffin@linaro.org>
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/usb/pd.h>
14 #include "gs101-pinctrl.h"
25 stdout-path = &serial_0;
[all …]
/linux/Documentation/networking/device_drivers/ethernet/intel/
H A Digb.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 Copyright(c) 1999-2018 Intel Corporation.
13 - Identifying Your Adapter
14 - Command Line Parameters
15 - Additional Configurations
16 - Support
34 There needs to be a <VAL#> for each network port in the system supported by
40 In this case, there are two network ports supported by igb in the system.
46 -------
47 :Valid Range: 0-7
[all …]
H A De100.rst1 .. SPDX-License-Identifier: GPL-2.0+
12 - In This Release
13 - Identifying Your Adapter
14 - Building and Installation
15 - Driver Configuration Parameters
16 - Additional Configurations
17 - Known Issues
18 - Support
25 Adapters. This driver includes support for Itanium(R)2-based systems.
31 - Native VLANs
[all …]
/linux/arch/arm/boot/dts/hisilicon/
H A Dhi3519.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/clock/hi3519-clock.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
19 compatible = "arm,cortex-a7";
24 gic: interrupt-controller@10300000 {
25 compatible = "arm,cortex-a7-gic";
[all …]
/linux/Documentation/arch/x86/
H A Dearlyprintk.rst1 .. SPDX-License-Identifier: GPL-2.0
7 Mini-HOWTO for using the earlyprintk=dbgp boot option with a
13 [host/target] <-------> [USB debug key] <-------> [client/console]
18 a) Host/target system needs to have USB debug port capability.
21 the lspci -vvv output::
23 # lspci -vvv
25 …00:1d.7 USB Controller: Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 (rev 03) (p…
27 …Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisIN…
28 …Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- I…
31 Region 0: Memory at fe227000 (32-bit, non-prefetchable) [size=1K]
[all …]
/linux/Documentation/devicetree/bindings/arm/
H A Dvexpress-config.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/vexpress-config.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andre Przywara <andre.przywara@arm.com>
13 This is a system control register block, acting as a bridge to the
14 platform's configuration bus via "system control" interface, addressing
15 devices with site number, position in the board stack, config controller,
16 function and device numbers - see motherboard's TRM for more details.
20 const: arm,vexpress,config-bus
[all …]
/linux/Documentation/admin-guide/
H A Dpstore-blk.rst1 .. SPDX-License-Identifier: GPL-2.0
7 ------------
10 block device and non-block device before the system crashes. You can get
13 mount -t pstore pstore /sys/fs/pstore
17 ---------------------
27 Configurations for driver are all about block device and non-block device,
31 -----------------------
51 #. /dev/<disk_name><decimal> represents the device number of partition - device
53 #. /dev/<disk_name>p<decimal> - same as the above; this form is used when disk
60 #. PARTUUID=00112233-4455-6677-8899-AABBCCDDEEFF represents the unique id of
[all …]
/linux/Documentation/core-api/
H A Ddebugging-via-ohci1394.rst2 Using physical DMA provided by OHCI-1394 FireWire controllers for debugging
6 ------------
9 to the OHCI-1394 specification which defines the controller to be a PCI
12 PCI-Bus master DMA after applying filters defined by the OHCI-1394 driver.
15 ask the OHCI-1394 controller to perform read and write requests on
16 physical system memory and, for read requests, send the result of
22 Retrieving a full system memory dump is also possible over the FireWire,
28 hardware such as x86, x86-64 and PowerPC.
34 Together with a early initialization of the OHCI-1394 controller for debugging,
36 buffer on to debug early boot problems in areas like ACPI where the system
[all …]
/linux/drivers/power/reset/
H A Darm-versatile-reboot.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/reboot.h>
36 /* Pointer to the system controller */
42 .compatible = "arm,core-module-integrator",
46 .compatible = "arm,core-module-versatile",
50 .compatible = "arm,realview-eb-syscon",
54 .compatible = "arm,realview-pb1176-syscon",
58 .compatible = "arm,realview-pb11mp-syscon",
62 .compatible = "arm,realview-pba8-syscon",
66 .compatible = "arm,realview-pbx-syscon",
[all …]
/linux/arch/arm/boot/dts/gemini/
H A Dgemini.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/clock/cortina,gemini-clock.h>
8 #include <dt-bindings/reset/cortina,gemini-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
16 compatible = "simple-bus";
17 interrupt-parent = <&intcon>;
20 compatible = "cortina,gemini-flash", "cfi-flash";
[all …]
/linux/Documentation/driver-api/nvdimm/
H A Dfirmware-activate.rst1 .. SPDX-License-Identifier: GPL-2.0
10 involves a reboot because it has implications for in-flight memory
24 - idle:
27 - armed:
30 - busy:
34 - overflow:
44 modifications of system memory. A value of 'live' attempts
51 does not require or inflict any quiesce period on the system to update
53 expect and injects a quiet period for the memory controller, but 'live'
55 assume the risk of racing firmware update with in-flight device and
[all …]

12345