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/illumos-gate/usr/src/uts/common/io/nxge/npi/
H A Dnpi_fflp.h90 /* have only 0xc, 0xd, 0xe and 0xf left for sw error codes */
127 * FCRAM_ENTRY_OPTIM: 8 bytes (a 64 bit write)
128 * FCRAM_ENTRY_EX_IP4: 32 bytes (4 X 64 bit write)
129 * FCRAM_ENTRY_EX_IP6: 56 bytes (7 X 64 bit write)
153 * FCRAM_ENTRY_OPTIM: 8 bytes (a 64 bit read)
154 * FCRAM_ENTRY_EX_IP4: 32 bytes (4 X 64 bit read )
155 * FCRAM_ENTRY_EX_IP6: 56 bytes (7 X 64 bit read )
194 * |-----------------| <-- H1
229 * H1--> |-----------------|
282 * Enable previously configured FCRAM partition
[all …]
H A Dnpi_rxdma.h246 * Enable 32 bit mode
263 * disable 32 bit mode
280 * Enable PIO access to shadow and prefetch memory.
283 * sane value (may be clear it) before re-enabling
536 uint8_t mbox_enable; /* Enable full (18b) header */
537 uint8_t full_hdr; /* Enable full (18b) header */
587 * num_pkts: Number of pkts processed by SW.
590 * num_bufs: Number of buffer processed by SW.
593 * NPI_FAILURE -
594 * NPI_RXDMA_OPCODE_INVALID -
[all …]
H A Dnpi.h80 /* Common SW errors code */
99 * Block identifier starts at bit 8.
104 * Port, channel and misc. information starts at bit 12.
131 * Bit 0 - 23: Address
132 * Bit 24 - 25: Function Number
133 * Bit 26 - 29: Instance Number
134 * Bit 30: Read/Write Direction bit
135 * Bit 31: Invalid bit
168 ENABLE, enumerator
/illumos-gate/usr/src/uts/common/io/e1000api/
H A De1000_api.c3 Copyright (c) 2001-2015, Intel Corporation
38 * e1000_init_mac_params - Initialize MAC function pointers
48 if (hw->mac.ops.init_params) { in e1000_init_mac_params()
49 ret_val = hw->mac.ops.init_params(hw); in e1000_init_mac_params()
56 ret_val = -E1000_ERR_CONFIG; in e1000_init_mac_params()
64 * e1000_init_nvm_params - Initialize NVM function pointers
74 if (hw->nvm.ops.init_params) { in e1000_init_nvm_params()
75 ret_val = hw->nvm.ops.init_params(hw); in e1000_init_nvm_params()
82 ret_val = -E1000_ERR_CONFIG; in e1000_init_nvm_params()
90 * e1000_init_phy_params - Initialize PHY function pointers
[all …]
H A De1000_82543.c3 Copyright (c) 2001-2015, Intel Corporation
81 * e1000_init_phy_params_82543 - Init PHY func ptrs.
86 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82543()
91 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_82543()
92 phy->type = e1000_phy_none; in e1000_init_phy_params_82543()
95 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_82543()
96 phy->ops.power_down = e1000_power_down_phy_copper; in e1000_init_phy_params_82543()
99 phy->addr = 1; in e1000_init_phy_params_82543()
100 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_82543()
101 phy->reset_delay_us = 10000; in e1000_init_phy_params_82543()
[all …]
H A De1000_defines.h3 Copyright (c) 2001-2015, Intel Corporation
44 #define E1000_WUC_APME 0x00000001 /* APM Enable */
45 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
51 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
52 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
53 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
54 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
55 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
56 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
57 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
[all …]
H A De1000_ich8lan.c3 Copyright (c) 2001-2015, Intel Corporation
36 * 82562G-2 10/100 Network Connection
38 * 82562GT-2 10/100 Network Connection
40 * 82562V-2 10/100 Network Connection
41 * 82566DC-2 Gigabit Network Connection
43 * 82566DM-2 Gigabit Network Connection
50 * 82567LM-2 Gigabit Network Connection
51 * 82567LF-2 Gigabit Network Connection
52 * 82567V-2 Gigabit Network Connection
53 * 82567LF-3 Gigabit Network Connection
[all …]
H A De1000_82575.c3 Copyright (c) 2001-2015, Intel Corporation
127 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
140 switch (hw->mac.type) { in e1000_sgmii_uses_mdio_82575()
161 * e1000_init_phy_params_82575 - Init PHY func ptrs.
166 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82575()
172 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic; in e1000_init_phy_params_82575()
173 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic; in e1000_init_phy_params_82575()
175 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_82575()
176 phy->type = e1000_phy_none; in e1000_init_phy_params_82575()
180 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_82575()
[all …]
H A De1000_mac.c3 Copyright (c) 2001-2015, Intel Corporation
43 * e1000_init_mac_ops_generic - Initialize MAC function pointers
46 * Setups up the function pointers to no-op functions
50 struct e1000_mac_info *mac = &hw->mac; in e1000_init_mac_ops_generic()
54 mac->ops.init_params = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
55 mac->ops.init_hw = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
56 mac->ops.reset_hw = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
57 mac->ops.setup_physical_interface = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
58 mac->ops.get_bus_info = e1000_null_ops_generic; in e1000_init_mac_ops_generic()
59 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie; in e1000_init_mac_ops_generic()
[all …]
/illumos-gate/usr/src/uts/common/io/igc/core/
H A Digc_i225.c1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
21 * igc_init_nvm_params_i225 - Init NVM func ptrs.
26 struct igc_nvm_info *nvm = &hw->nvm; in igc_init_nvm_params_i225()
35 * Added to a constant, "size" becomes the left-shift value in igc_init_nvm_params_i225()
46 nvm->word_size = 1 << size; in igc_init_nvm_params_i225()
47 nvm->opcode_bits = 8; in igc_init_nvm_params_i225()
48 nvm->delay_usec = 1; in igc_init_nvm_params_i225()
49 nvm->type = igc_nvm_eeprom_spi; in igc_init_nvm_params_i225()
52 nvm->page_size = eecd & IGC_EECD_ADDR_BITS ? 32 : 8; in igc_init_nvm_params_i225()
[all …]
H A Digc_defines.h1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
16 #define IGC_WUC_APME 0x00000001 /* APM Enable */
17 #define IGC_WUC_PME_EN 0x00000002 /* PME Enable */
23 #define IGC_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
24 #define IGC_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
25 #define IGC_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
26 #define IGC_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
27 #define IGC_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
28 #define IGC_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
[all …]
H A Digc_api.c1 /*-
4 * SPDX-License-Identifier: BSD-3-Clause
10 * igc_init_mac_params - Initialize MAC function pointers
20 if (hw->mac.ops.init_params) { in igc_init_mac_params()
21 ret_val = hw->mac.ops.init_params(hw); in igc_init_mac_params()
28 ret_val = -IGC_ERR_CONFIG; in igc_init_mac_params()
36 * igc_init_nvm_params - Initialize NVM function pointers
46 if (hw->nvm.ops.init_params) { in igc_init_nvm_params()
47 ret_val = hw->nvm.ops.init_params(hw); in igc_init_nvm_params()
54 ret_val = -IGC_ERR_CONFIG; in igc_init_nvm_params()
[all …]
/illumos-gate/usr/src/uts/common/io/ntxn/
H A Dunm_inc.h72 /* ------------------------------------------------------------------------ */
74 /* ------------------------------------------------------------------------ */
507 * ====================== BASE ADDRESSES ON-CHIP ======================
508 * Base addresses of major components on-chip.
509 * ====================== BASE ADDRESSES ON-CHIP ======================
515 * Imbus address bit used to indicate a host address. This bit is
816 #define P2_MIN_TICKS_PER_SEC (P2_TICKS_PER_SEC-10)
871 tx_enable:1, /* 1:enable frame xmit, 0:disable */
872 tx_synched:1, /* R/O: xmit enable synched to xmit stream */
873 rx_enable:1, /* 1:enable frame recv, 0:disable */
[all …]
/illumos-gate/usr/src/uts/sun4v/io/n2piupc/
H A Dn2piupc_biterr.h33 * "Virtual register" definitions for the bit error performance counters.
35 * The N2 PIU presents two bit error counters. Bit 63 on the first counter
36 * serves as an enable for all bit error counters. Bit 62 serves as a clear
37 * for all the bit error counters.
39 * Busstat doesn't play well with a register that has counters, enable and
53 * lanes 0-7 or all lanes together
55 * SW_N2PIU_BITERR_CLR Setting bit 62 here clears all biterr
56 * counters (write-only)
58 * SW_N2PIU_BITERR_SEL Bit 63 is overall biterr enable.
59 * Bits 0-3 are event select for counter 2
[all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/
H A D57712_reg.h3 …//ACCESS:RW DataWidth:0x2 Description: Defines the number of sets - 3 - 256 ;2- 128; 1- 64; 0- 32
5 …ne FIFO full bit; RCPL FIFO full bit; TCPL FIFO full bit; IREQ full bit; PLKP FIFO full bit; MLKP …
6 …IFO empty bit; RCPL FIFO empty bit; TCPL FIFO empty bit; IREQ empty bit; PLKP FIFO empty bit; MLKP…
7 … 0x110010UL //ACCESS:RW DataWidth:0x1 Description: WaitIfMiss configuration bit
8 … 0x110014UL //ACCESS:RW DataWidth:0x1 Description: WaitTransPending cofiguration bit
9 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
10 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
11 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
12 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
13 …all (on the second event). The order of the vectors is 0-Mlkp;1-Plkp;2-Ireq;3-Tcpl;4-SPA-Done;5-Rc…
[all …]
/illumos-gate/usr/src/uts/common/sys/
H A Dasy.h47 #define ASY_BUS_UNKNOWN (-1)
78 ASY_IER, /* Interrupt Enable Register (R/W) */
111 ASY_FCL, /* Flow Control Low-Level (R/W) */
112 ASY_FCH, /* Flow Control High-Level (R/W) */
118 ASY_NMR, /* Nine-Bit Mode Register (R/W) */
124 * INTEL 8210-A/B & 16450/16550 Registers Structure.
127 /* Interrupt Enable Register */
140 #define ASY_FCR_THR_TR0 0x10 /* transmitter trigger level bit 0 (16650) */
141 #define ASY_FCR_THR_TR1 0x20 /* transmitter trigger level bit 1 (16650) */
142 #define ASY_FCR_FIFO64 0x20 /* 64 byte FIFO enable (16750) */
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/illumos-gate/usr/src/uts/common/io/chxge/
H A Doschtoe.h30 * Copyright (C) 2003-2005 Chelsio Communications. All rights reserved.
58 #define CFGDMP_ISRC 0x00001000 /* dump ISR 32 bit cause */
67 #define CFGMD_PROFILE 0x00200000 /* Enable driver profiling */
74 #define CFGMD_TUNNEL 0x10000000 /* Global tunnel mode ( 0-offload mode ) */
75 #define CFGMD_144BIT 0x20000000 /* Puts MC5 in 144 bit mode */
90 * 5-auto-neg
91 * 2-1000Gbps(force);
92 * 1-100Gbps(force);
93 * 0-10Gbps(force)
97 uint32_t num_of_ports; /* Set the number of ports [1-4] */
[all …]
/illumos-gate/usr/src/uts/common/io/1394/adapters/
H A Dhci1394_csr.c23 * Copyright (c) 1999-2000 by Sun Microsystems, Inc.
30 * SW. The HW implemented CSR registers are in hci1394_ohci.c
34 * IEEE 1394-1995
39 * NOTE: A read/write to a CSR SW based register will first go to the Services
42 * which are implemented in SW.
76 * Split Timeout Registers are implemented (bit 15)
77 * This node uses 64-bit addressing (bit 9)
78 * This node uses fixed addressing scheme (bit 8)
97 * Initialize CSR state and CSR SW based registers.
117 csr->csr_drvinfo = drvinfo; in hci1394_csr_init()
[all …]
/illumos-gate/usr/src/uts/common/io/e1000g/
H A De1000g_tx.c9 * Copyright(c) 1999 - 2009 Intel Corporation. All rights reserved.
83 * e1000g_free_tx_swpkt - free up the tx sw packet
86 * transmit sw packet. And reset the sw packet data.
91 switch (packet->data_transfer_type) { in e1000g_free_tx_swpkt()
93 packet->tx_buf->len = 0; in e1000g_free_tx_swpkt()
97 dvma_unload(packet->tx_dma_handle, 0, -1); in e1000g_free_tx_swpkt()
101 (void) ddi_dma_unbind_handle(packet->tx_dma_handle); in e1000g_free_tx_swpkt()
108 * The mblk has been stripped off the sw packet in e1000g_free_tx_swpkt()
111 ASSERT(packet->mp == NULL); in e1000g_free_tx_swpkt()
113 packet->data_transfer_type = USE_NONE; in e1000g_free_tx_swpkt()
[all …]
/illumos-gate/usr/src/grub/grub-0.97/netboot/
H A De1000_hw.h4 Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
291 /* MAC decode size is 128K - This is the size of BAR0 */
309 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
311 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
329 * Set/Read Register. Each bit is documented below:
338 * Set/Read Register. Each bit is documented below:
355 * E1000_RAR_ENTRIES - 1 multicast addresses.
372 /* Receive Decriptor bit definitions */
[all …]
/illumos-gate/usr/src/uts/common/io/yge/
H A Dyge.h12 * are provided to you under the BSD-type license terms provided
17 * - Redistributions of source code must retain the above copyright
19 * - Redistributions in binary form must reproduce the above
23 * - Neither the name of Marvell nor the names of its contributors
57 * D-Link PCI vendor ID
91 * D-Link gigabit ethernet device ID
97 #define BIT(n) (1U << n) macro
102 #define PCI_BASE_1ST 0x10 /* 32 bit 1st Base address */
103 #define PCI_BASE_2ND 0x14 /* 32 bit 2nd Base address */
104 #define PCI_OUR_REG_1 0x40 /* 32 bit Our Register 1 */
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/illumos-gate/usr/src/uts/common/io/bnx/570x/common/include/
H A Dserdes.h2 * Copyright 2014-2017 Cavium, Inc.
9 * at http://opensource.org/licenses/CDDL-1.0
48 /* Write of '1' initiate auto-negotiation and will self clear
49 when auto-negotiation
77 /* Value of '1' indicates auto-negotiation complete. */
78 /* Value of '0' indicates auto-negotiation is in progress. */
81 /* This bit latches high until read. */
83 /* Value of '1' indicates auto-negotiation capable. */
87 /* This bit latches low until read. */
115 /* auto-negotiation error */
[all …]
/illumos-gate/usr/src/uts/common/io/hxge/
H A Dhpi.h56 /* Common SW errors code */
73 * Block identifier starts at bit 8.
78 * Port, channel and misc. information starts at bit 12.
103 * Bit 0 - 23: Address
104 * Bit 24 - 25: Function Number
105 * Bit 26 - 29: Instance Number
106 * Bit 30: Read/Write Direction bit
107 * Bit 31: Invalid bit
132 ENABLE, enumerator
/illumos-gate/usr/src/uts/common/io/ixgbe/core/
H A Dixgbe_82599.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2017, Intel Corporation
64 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_mac_link_ops_82599()
69 * enable the laser control functions for SFP+ fiber in ixgbe_init_mac_link_ops_82599()
72 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && in ixgbe_init_mac_link_ops_82599()
74 mac->ops.disable_tx_laser = in ixgbe_init_mac_link_ops_82599()
76 mac->ops.enable_tx_laser = in ixgbe_init_mac_link_ops_82599()
78 mac->ops.flap_tx_laser = ixgbe_flap_tx_laser_multispeed_fiber; in ixgbe_init_mac_link_ops_82599()
81 mac->ops.disable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
82 mac->ops.enable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
[all …]
H A Dixgbe_common.c2 SPDX-License-Identifier: BSD-3-Clause
4 Copyright (c) 2001-2017, Intel Corporation
65 * ixgbe_init_ops_generic - Inits function ptrs
72 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; in ixgbe_init_ops_generic()
73 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_ops_generic()
79 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic; in ixgbe_init_ops_generic()
80 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */ in ixgbe_init_ops_generic()
82 eeprom->ops.read = ixgbe_read_eerd_generic; in ixgbe_init_ops_generic()
83 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic; in ixgbe_init_ops_generic()
85 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic; in ixgbe_init_ops_generic()
[all …]

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