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/freebsd/sys/contrib/openzfs/tests/zfs-tests/tests/functional/rsend/
H A Drsend-exclude_001_pos.ksh51 log_must zfs create $sendfs/ds1/sub1
52 log_must zfs create $sendfs/ds1/sub1/sub2
54 log_must zfs create $sendfs/ds2/sub1
55 log_must zfs create $sendfs/ds2/sub1/sub3
60 # Now we'll send $sendfs@A, but exclude ds1/sub1
61 log_must zfs send -R --exclude ds1/sub1 $sendfs@A > $BACKDIR/stream1
64 lost_mustnot grep -q ds1/sub1/sub2 $BACKDIR/list
65 lost_mustnot grep -q ds1/sub1 $BACKDIR/list
66 log_must grep -q ds2/sub1 $BACKDIR/list
H A Drsend-exclude_002_pos.ksh52 log_must zfs create $sendfs/ds1/sub1
53 log_must zfs create $sendfs/ds1/sub1/sub2
55 log_must zfs create $sendfs/ds2/sub1
56 log_must zfs create $sendfs/ds2/sub1/sub3
71 log_must grep -q ds2/sub1 $BACKDIR/list
/freebsd/contrib/bmake/unit-tests/
H A Dcmdline.mk6 SUB1= a7b41170-53f8-4cc2-bc5c-e4c3dd93ec45 # just a random UUID
8 MAKE_CMD= env TMPBASE=${TMPBASE}/${SUB1} ${.MAKE} -f ${MAKEFILE} -r
10 DIR12= ${TMPBASE}/${SUB1}/${SUB2}
31 # The SUB1 in the resulting path comes from the environment variable TMPBASE,
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DEvergreenInstructions.td311 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), $data, sub0), $ptr), sub1)>;
322 $ptr), sub1)>;
439 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub1)),
440 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub1)),
441 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub1))), sub1)
458 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub1)),
459 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub1)),
460 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub1))), sub1)
471 (i32 (EXTRACT_SUBREG R600_Reg64:$src1, sub1)))
479 (i32 (EXTRACT_SUBREG R600_Reg64:$src0, sub1)),
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H A DSIInstructions.td1387 (V_BCNT_U32_B32_e64 (i32 (EXTRACT_SUBREG i64:$src, sub1)),
1389 (i32 (V_MOV_B32_e32 (i32 0))), sub1)
1464 (REG_SEQUENCE RC, $elem, sub0, (elem_type (EXTRACT_SUBREG $vec, sub1)), sub1)
1469 (REG_SEQUENCE RC, (elem_type (EXTRACT_SUBREG $vec, sub0)), sub0, $elem, sub1)
1943 (f32 (COPY_TO_REGCLASS (S_XOR_B32 (i32 (EXTRACT_SUBREG $src, sub1)),
1945 SReg_32)), sub1))
1954 (f32 (COPY_TO_REGCLASS (S_AND_B32 (i32 (EXTRACT_SUBREG $src, sub1)),
1956 SReg_32)), sub1))
1965 (f32 (COPY_TO_REGCLASS (S_OR_B32 (i32 (EXTRACT_SUBREG $src, sub1)),
1967 SReg_32)), sub1))
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H A DR600OptimizeVectorRegisters.cpp14 /// %5 = REG_SEQ %1, sub0, %2, sub1, %3, sub2, undef, sub3
16 /// %7 = REG_SEQ %1, sub0, %3, sub1, undef, sub2, %4, sub3
17 /// (swizzable Inst) %7, SwizzleMask : sub0, sub1, sub2, sub3
20 /// %5 = REG_SEQ %1, sub0, %2, sub1, %3, sub2, undef, sub3
23 /// (swizzable Inst) %7, SwizzleMask : sub0, sub2, sub1, sub3
H A DAMDGPUISelDAGToDAG.cpp432 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)}; in buildSMovImm64()
542 unsigned Src0SubReg = Mask[0] & 1 ? AMDGPU::sub1 : AMDGPU::sub0; in SelectVectorShuffle()
543 unsigned Src1SubReg = Mask[1] & 1 ? AMDGPU::sub1 : AMDGPU::sub0; in SelectVectorShuffle()
565 if (N->isDivergent() && Src0SubReg == AMDGPU::sub1 && in SelectVectorShuffle()
573 Src0SubReg == AMDGPU::sub1 ? SISrcMods::OP_SEL_0 : SISrcMods::NONE; in SelectVectorShuffle()
575 Src1SubReg == AMDGPU::sub1 ? SISrcMods::OP_SEL_0 : SISrcMods::NONE; in SelectVectorShuffle()
604 ResultElt1, CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)}; in SelectVectorShuffle()
694 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in Select()
971 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in SelectADD_SUB_I64() local
976 DL, MVT::i32, LHS, Sub1); in SelectADD_SUB_I64()
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H A DR600RegisterInfo.td23 let SubRegIndices = [sub0, sub1, sub2, sub3];
32 let SubRegIndices = [sub0, sub1];
H A DGCNPreRAOptimizations.cpp12 /// undef %0.sub1:sreg_64 = S_MOV_B32 1
177 case AMDGPU::sub1: in processReg()
H A DSIRegisterInfo.td157 let SubRegIndices = [sub0, sub1];
167 let SubRegIndices = [sub0, sub1];
197 let SubRegIndices = [sub0, sub1];
221 let SubRegIndices = [sub0, sub1];
254 let SubRegIndices = [sub0, sub1];
264 let SubRegIndices = [sub0, sub1];
273 let SubRegIndices = [sub0, sub1];
292 let SubRegIndices = [sub0, sub1];
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRenameIndependentSubregs.cpp13 /// %0:sub1 = ...
17 /// use %0:sub1
18 /// sub0 and sub1 are never used together, and we have two independent sub0
21 /// %1:sub1<read-undef> = ...
22 /// use %1:sub1
23 /// %2:sub1<read-undef> = ...
24 /// use %2:sub1
H A DExpandFp.cpp249 /// %sub1 = sub nuw nsw i32 64, %cast
255 /// switch i32 %sub1, label %sw.default [
285 /// %spec.select56 = select i1 %tobool.not, i32 %sub2, i32 %sub1
381 Value *Sub1 = Builder.CreateSub(Builder.getIntN(BitWidthNew, BitWidth), in expandIToFP() local
386 Sub1, Builder.getIntN(BitWidthNew, FPMantissaWidth + 1)); in expandIToFP()
391 llvm::SwitchInst *SI = Builder.CreateSwitch(Sub1, SwDefault); in expandIToFP()
460 ExtractT62 = Builder.CreateTrunc(Sub1, Builder.getIntNTy(64)); in expandIToFP()
500 E0->addIncoming(Sub1, IfThen20); in expandIToFP()
/freebsd/contrib/libarchive/libarchive/test/
H A Dtest_read_disk_directory_traversals.c98 assertMakeDir("dir1/sub1", 0755); in test_basic()
99 assertMakeFile("dir1/sub1/file1", 0644, "0123456789"); in test_basic()
103 assertMakeDir("dir1/sub2/sub1", 0755); in test_basic()
147 "dir1/sub1") == 0) { in test_basic()
151 "dir1/sub1/file1") == 0) { in test_basic()
197 "dir1/sub2/sub1") == 0) { in test_basic()
275 L"dir1/sub1") == 0) { in test_basic()
279 L"dir1/sub1/file1") == 0) { in test_basic()
325 L"dir1/sub2/sub1") == 0) { in test_basic()
405 /* dir1/sub1 */ in test_basic()
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/freebsd/share/doc/papers/kerntune/
H A D2.t107 1.50 1.00 20/40 \ \ \s-1SUB1\s+1 <cycle1> [4]
175 The routine \s-1EXAMPLE\s+1 calls routine \s-1SUB1\s+1 twenty times, \s-1SUB2\s+1 once,
180 Because \s-1SUB1\s+1 is a member of \fIcycle 1\fR,
H A Dfig2.pic33 ellipse ht .3i wid .5i "\s-1SUB1\s+1" at 1st ellipse - (0i,1i)
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h56 /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
58 /// - %1:sub1, sub0
59 /// - %2<:0>, sub1
72 /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
73 /// - %1:sub1, sub0
86 /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
88 /// - InsertedReg: %1:sub1, sub3
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DDetectDeadLanes.h21 /// %2 = REG_SEQUENCE %0, sub0, %1, sub1
22 /// %3 = EXTRACT_SUBREG %2, sub1
H A DLiveInterval.h863 /// V1.sub1:<2 x s32> = COPY V2.sub3:<4 x s32>
864 /// We do that by choosing a class where sub1:<2 x s32> and sub3:<4 x s32>
866 /// Put differently we align V2's sub3 with V1's sub1:
867 /// V2: sub0 sub1 sub2 sub3
868 /// V1: <offset> sub0 sub1
871 /// V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32>
872 /// => V1.(composed sub2 with sub1):<4 x s32> = COPY V2.sub3:<4 x s32>
/freebsd/share/doc/psd/18.gprof/
H A Dpresent.me72 1.50 1.00 20/40 \ \ \s-1SUB1\s+1 <cycle1> [4]
151 The routine \s-1EXAMPLE\s+1 calls routine \s-1SUB1\s+1 twenty times, \s-1SUB2\s+1 once,
156 Because \s-1SUB1\s+1 is a member of \fIcycle 1\fR,
H A Dpres1.pic32 ellipse ht .3i wid .5i "\s-1SUB1\s+1" at 1st ellipse - (0i,1i)
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp220 SDValue Sub1 = in selectInlineAsm() local
224 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in selectInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp252 SDValue Sub1 = CurDAG->getTargetExtractSubreg(SP::sub_odd, dl, MVT::i32, in tryInlineAsm() local
256 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1)); in tryInlineAsm()
/freebsd/sys/contrib/device-tree/Bindings/net/wireless/
H A Dmarvell-8xxx.txt28 "marvell,caldata-txpwrlimit-5g-sub1" (length = 688).
H A Dmarvell,sd8787.yaml47 marvell,caldata-txpwrlimit-5g-sub1:
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/
H A DCombine.td1730 (match (G_SUB $sub1, $A, $B),
1732 (G_ADD $root, $sub1, $sub2)),
1738 (match (G_SUB $sub1, $A, $B),
1740 (G_ADD $root, $sub1, $sub2)),
1747 (G_SUB $sub1, $B, $add1),
1748 (G_ADD $root, $A, $sub1)),
1755 (G_SUB $sub1, $B, $add1),
1756 (G_ADD $root, $A, $sub1)),
1784 (G_SUB $sub1, $A, $c1),
1785 (G_SUB $root, $sub1, $c2):$root,
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