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/freebsd/sys/contrib/device-tree/Bindings/net/
H A Daltr,socfpga-stmmac.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/altr,socfpga-stmmac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Altera SOCFPGA SoC DWMAC controller
10 - Matthew Gerlach <matthew.gerlach@altera.com>
13 This binding describes the Altera SOCFPGA SoC implementation of the
16 # TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that
24 - altr,socfpga-stmmac
25 - altr,socfpga-stmmac-a10-s10
[all …]
H A Dsocfpga-dwmac.txt1 Altera SOCFPGA SoC DWMAC controller
3 This is a variant of the dwmac/stmmac driver an inherits all descriptions
4 present in Documentation/devicetree/bindings/net/stmmac.txt.
9 - compatible : For Cyclone5/Arria5 SoCs it should contain
10 "altr,socfpga-stmmac". For Arria10/Agilex/Stratix10 SoCs
11 "altr,socfpga-stmmac-a10-s10".
13 designware version numbers documented in stmmac.txt
14 - altr,sysmgr-syscon : Should be the phandle to the system manager node that
20 - altr,f2h_ptp_ref_clk use f2h_ptp_ref_clk instead of default eosc1 clock
24 altr,emac-splitter: Should be the phandle to the emac splitter soft IP node if
[all …]
/freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/
H A Dsocfpga_arria10.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/reset/altr,rst-mgr-a10.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 #address-cells = <1>;
15 #size-cells = <0>;
16 enable-method = "altr,socfpga-a10-smp";
19 compatible = "arm,cortex-a9";
22 next-level-cache = <&L2>;
[all …]
H A Dsocfpga.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/reset/altr,rst-mgr.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
22 #address-cells = <1>;
23 #size-cells = <0>;
24 enable-metho
[all...]
/freebsd/sys/contrib/device-tree/src/arm64/intel/
H A Dsocfpga_agilex.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/agilex-clock.h>
13 compatible = "intel,socfpga-agilex";
14 #address-cells = <2>;
15 #size-cells = <2>;
17 reserved-memory {
[all …]
/freebsd/sys/contrib/device-tree/src/arm64/altera/
H A Dsocfpga_stratix10.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
7 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/clock/stratix10-clock.h>
12 compatible = "altr,socfpga-stratix10";
13 #address-cells = <2>;
14 #size-cells = <2>;
16 reserved-memory {
17 #address-cells = <2>;
[all …]
/freebsd/sys/dev/dwc/
H A Dif_dwc_socfpga.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
8 * Technology) under DARPA contract HR0011-18-C-0016 ("ECATS"), as part of the
62 if (!ofw_bus_is_compatible(dev, "altr,socfpga-stmmac")) in if_dwc_socfpga_probe()
65 device_set_desc(dev, "Altera SOCFPGA Ethernet MAC"); in if_dwc_socfpga_probe()
84 if (ofw_bus_node_is_compatible(root, "altr,socfpga-stratix10")) in if_dwc_socfpga_mii_clk()