Home
last modified time | relevance | path

Searched +full:sifive +full:- +full:fu540 +full:- +full:prci (Results 1 – 7 of 7) sorted by relevance

/freebsd/sys/contrib/device-tree/src/riscv/sifive/
H A Dfu540-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu540
180 prci: clock-controller@10000000 { global() label
[all...]
H A Dfu740-c000.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020 SiFive, Inc */
4 /dts-v1/;
6 #include <dt-bindings/clock/sifive-fu740-prci
181 prci: clock-controller@10000000 { global() label
[all...]
/freebsd/sys/contrib/device-tree/Bindings/clock/sifive/
H A Dfu540-prci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 SiFive, Inc.
4 ---
5 $id: http://devicetree.org/schemas/clock/sifive/fu540-prci.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
11 - Paul Walmsley <paul.walmsley@sifive.com>
14 On the FU540 family of SoCs, most system-wide clock and reset integration
15 is via the PRCI IP block.
17 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
[all …]
H A Dfu540-prci.txt1 SiFive FU540 PRCI bindings
3 On the FU540 family of SoCs, most system-wide clock and reset integration
4 is via the PRCI IP block.
7 - compatible: Should be "sifive,<chip>-prci". Only one value is
8 supported: "sifive,fu540-c000-prci"
9 - reg: Should describe the PRCI's register target physical address region
10 - clocks: Should point to the hfclk device tree node and the rtcclk
11 device tree node. The RTC clock here is not a time-of-day clock,
12 but is instead a high-stability clock source for system timers
14 - #clock-cells: Should be <1>
[all …]
/freebsd/sys/contrib/device-tree/Bindings/serial/
H A Dsifive-serial.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/serial/sifive-serial.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive asynchronous serial interface (UART)
10 - Pragnesh Patel <pragnesh.patel@sifive.com>
11 - Paul Walmsley <paul.walmsley@sifive.com>
12 - Palmer Dabbelt <palmer@sifive.com>
15 - $ref: serial.yaml#
20 - enum:
[all …]
/freebsd/sys/contrib/device-tree/Bindings/gpio/
H A Dsifive,gpio.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/sifive,gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SiFive GPIO controller
10 - Paul Walmsley <paul.walmsley@sifive.com>
15 - enum:
16 - sifive,fu540-c000-gpio
17 - sifive,fu740-c000-gpio
18 - canaan,k210-gpiohs
[all …]
/freebsd/sys/riscv/sifive/
H A Dsifive_prci.c1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
85 #define PRCI_LOCK(sc) mtx_lock(&(sc)->mtx)
86 #define PRCI_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
87 #define PRCI_ASSERT_LOCKED(sc) mtx_assert(&(sc)->mtx, MA_OWNED);
88 #define PRCI_ASSERT_UNLOCKED(sc) mtx_assert(&(sc)->mtx, MA_NOTOWNED);
97 /* Called devicesresetreg on the FU540 */
101 bus_space_read_4((_sc)->bst, (_sc)->bsh, (_reg))
103 bus_space_write_4((_sc)->bst, (_sc)->bsh, (_reg), (_val))
164 /* FU540 clock numbers */
[all …]