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/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYInstrInfo16Instr.td178 def MOV16 : CSKY16Inst<AddrModeNone, (outs sGPR:$rz), (ins sGPR:$rx),
191 (outs sGPR:$rz), (ins CARRY:$ca), "mvcv16\t$rz", []> {
218 let Pattern = [(brind sGPR:$rx)];
323 def TST16 : CSKY16Inst<AddrModeNone, (outs CARRY:$ca), (ins sGPR:$rx, sGPR:$ry),
335 def TSTNBZ16 : CSKY16Inst<AddrModeNone, (outs CARRY:$ca), (ins sGPR:$rx),
420 def ISEL16 : CSKYPseudo<(outs sGPR:$dst),
421 (ins CARRY:$cond, sGPR:$src1, sGPR:$src2),
423 [(set sGPR:$dst, (select CARRY:$cond, sGPR:$src1, sGPR:$src2))]>;
452 def : Pat<(sext_inreg sGPR:$src, i8), (SEXTB16 sGPR:$src)>;
453 def : Pat<(sext_inreg sGPR:$src, i16), (SEXTH16 sGPR:$src)>;
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H A DCSKYInstrFormats16Instr.td41 AddrModeNone, (outs sGPR:$rz), (ins sGPR:$rZ, sGPR:$rx), !strconcat(opstr, "\t$rz, $rx"),
42 [(set sGPR:$rz, (opnode sGPR:$rZ, sGPR:$rx))]> {
54 AddrModeNone, (outs sGPR:$rz), (ins sGPR:$rZ, sGPR:$rx), !strconcat(opstr, "\t$rz, $rx"),
67 AddrModeNone, (outs sGPR:$rz, CARRY:$cout),
68 (ins sGPR:$rZ, sGPR:$rx, CARRY:$cin), !strconcat(opstr, "\t$rz, $rx"), []> {
80 AddrModeNone, (outs sGPR:$rz), (ins sGPR:$rx), !strconcat(opstr, "\t$rz, $rx"),
92 AddrModeNone, (outs sGPR:$rz), (ins sGPR:$rx), !strconcat(opstr, "\t$rz"),
105 AddrModeNone, (outs CARRY:$ca), (ins sGPR:$rx, sGPR:$ry), !strconcat(opstr, "\t$rx, $ry"),
118 AddrModeNone, (outs), (ins sGPR:$rx), !strconcat(opstr, "\t$rx"), []> {
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURegBankLegalize.cpp15 /// For example vgpr S64 G_AND requires lowering to S32 while sgpr S64 does not.
16 /// Eliminate sgpr S1 by lowering to sgpr S32.
147 // This is a cross bank copy, sgpr S1 to lane mask. in tryCombineCopy()
149 // %Src:sgpr(s1) = G_TRUNC %TruncS32Src:sgpr(s32) in tryCombineCopy()
150 // %Dst:lane-mask(s1) = COPY %Src:sgpr(s1) in tryCombineCopy()
152 // %Dst:lane-mask(s1) = G_AMDGPU_COPY_VCC_SCC %TruncS32Src:sgpr(s32) in tryCombineCopy()
156 "sgpr S1 must be result of G_TRUNC of sgpr S32"); in tryCombineCopy()
185 // %Src:sgpr(S1) = G_TRUNC %TruncSrc in tryCombineS1AnyExt()
186 // %Dst = G_ANYEXT %Src:sgpr(S1) in tryCombineS1AnyExt()
239 // Search through MRI for virtual registers with sgpr register bank and S1 LLT.
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H A DSIFixSGPRCopies.cpp1 //===- SIFixSGPRCopies.cpp - Remove potential VGPR => SGPR copies ---------===//
10 /// Copies from VGPR to SGPR registers are illegal and the register coalescer
13 /// Register Class <vsrc> is the union of <vgpr> and <sgpr>
16 /// %0 <sgpr> = SCALAR_INST
17 /// %1 <vsrc> = COPY %0 <sgpr>
32 /// %0 <sgpr> = SCALAR_INST
39 /// %4 <sgpr> = PHI %0 <sgpr>, <%bb.0>, %3 <vsrc>, <%bb.1>
40 /// %5 <vgpr> = VECTOR_INST %4 <sgpr>
42 /// Now that the result of the PHI instruction is an SGPR, the register
44 /// <sgpr> so we end up with final code like this:
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H A DAMDGPUCallingConv.td26 !foreach(i, !range(4, 30), !cast<Register>("SGPR"#i)) // SGPR4-29
50 !foreach(i, !range(0, 44), !cast<Register>("SGPR"#i)) // SGPR0-43
62 !foreach(i, !range(0, 44), !cast<Register>("SGPR"#i)) // SGPR0-43
98 (add (sequence "SGPR%u", 30, 39),
99 (sequence "SGPR%u", 48, 55),
100 (sequence "SGPR%u", 64, 71),
101 (sequence "SGPR%u", 80, 87),
102 (sequence "SGPR%u", 96, 105))
106 (add (sequence "SGPR%u", 4, 31), (sequence "SGPR%u", 64, 105))
138 !foreach(i, !range(0, 30), !cast<Register>("SGPR"#i)) // SGPR0-29
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H A DAMDGPUWaitSGPRHazards.cpp1 //===- AMDGPUWaitSGPRHazards.cpp - Insert waits for SGPR read hazards -----===//
10 /// Insert s_wait_alu instructions to mitigate SGPR read hazards on GFX12.
23 #define DEBUG_TYPE "amdgpu-wait-sgpr-hazards"
26 "amdgpu-sgpr-hazard-wait", cl::init(true), cl::Hidden,
27 cl::desc("Enable required s_wait_alu on SGPR hazards"));
30 "amdgpu-sgpr-hazard-boundary-cull", cl::init(false), cl::Hidden,
34 GlobalCullSGPRHazardsAtMemWait("amdgpu-sgpr-hazard-mem-wait-cull",
39 "amdgpu-sgpr-hazard-mem-wait-cull-threshold", cl::init(8), cl::Hidden,
59 // Return the numeric ID 0-127 for a given SGPR.
120 std::bitset<64> Tracked; // SGPR banks ever read by VALU
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H A DAMDKernelCodeT.h75 /// Enable the setup of the SGPR user data registers
83 /// SGPR user data registers enabled up to 16).
325 /// The order of the SGPR registers is defined, but the Finalizer can specify
329 /// enabled register is SGPR1 etc.; disabled registers do not have an SGPR
339 /// SGPR register initial state is defined as follows:
342 /// Number of User SGPR registers: 4. V# that can be used, together with
369 /// Number of User SGPR registers: 2. 64 bit address of AQL dispatch packet
373 /// Number of User SGPR registers: 2. 64 bit address of AmdQueue object for
377 /// Number of User SGPR registers: 2. 64 bit address of Kernarg segment. This
382 /// Number of User SGPR registers: 2. 64 bit Dispatch ID of the dispatch
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H A DSILowerSGPRSpills.cpp9 // Handle SGPR spills. This pass takes the place of PrologEpilogInserter for all
10 // SGPR spills, so must insert CSR SGPR spills as well as expand them.
12 // This pass must never create new SGPR virtual registers.
30 #define DEBUG_TYPE "si-lower-sgpr-spills"
93 "SI lower SGPR spill instructions", false, false)
98 "SI lower SGPR spill instructions", false, false)
400 // First, expose any CSR SGPR spills. This is mostly the same as what PEI in run()
424 // Process all SGPR spills before frame offsets are finalized. Ideally SGPRs in run()
427 // This operates under the assumption that only other SGPR spills are users in run()
469 "failed to spill SGPR to physical VGPR lane when allocated"); in run()
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H A DSIFrameLowering.cpp73 MachineFunction &MF, LiveRegUnits &LiveUnits, Register SGPR, in getVGPRSpillLaneOrTempRegister() argument
84 // We need to save and restore the given SGPR. in getVGPRSpillLaneOrTempRegister()
87 // 1: Try to save the given register into an unused scratch SGPR. The in getVGPRSpillLaneOrTempRegister()
89 // certain cases we skip copy to scratch SGPR. in getVGPRSpillLaneOrTempRegister()
101 // SGPR, so we're forced to take another VGPR to use for the spill. in getVGPRSpillLaneOrTempRegister()
103 SGPR, PrologEpilogSGPRSaveRestoreInfo( in getVGPRSpillLaneOrTempRegister()
107 dbgs() << printReg(SGPR, TRI) << " requires fallback spill to " in getVGPRSpillLaneOrTempRegister()
116 SGPR, in getVGPRSpillLaneOrTempRegister()
119 << printReg(SGPR, TRI) << '\n'); in getVGPRSpillLaneOrTempRegister()
123 SGPR, PrologEpilogSGPRSaveRestoreInfo( in getVGPRSpillLaneOrTempRegister()
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H A DSIRegisterInfo.td303 // SGPR registers
305 defm SGPR#Index :
355 (add (sequence "SGPR%u_LO16", 0, 105))> {
363 (add (sequence "SGPR%u_HI16", 0, 105))> {
370 // SGPR 32-bit registers
372 (add (sequence "SGPR%u", 0, 105))> {
373 // Give all SGPR classes higher priority than VGPR classes, because
380 // SGPR 64-bit registers
383 // SGPR 96-bit registers.
386 // SGPR 128-bit registers
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H A DGCNRegPressure.h11 /// by bookkeeping number of SGPR/VGPRs used, weights for large SGPR/VGPRs. It
32 enum RegKind { SGPR, VGPR, AGPR, TOTAL_KINDS }; enumerator
38 bool empty() const { return !Value[SGPR] && !Value[VGPR] && !Value[AGPR]; } in empty()
43 unsigned getSGPRNum() const { return Value[SGPR]; } in getSGPRNum()
70 unsigned getSGPRTuplesWeight() const { return Value[TOTAL_KINDS + SGPR]; } in getSGPRTuplesWeight()
97 /// 2. Less spilling (first preference to VGPR spills, then to SGPR spills)
99 /// determine that SGPR pressure is not important)
101 /// determine that SGPR pressure is not important)
H A DSIRegisterInfo.h83 /// Return the largest available SGPR aligned to \p Align for the register
193 MachineBasicBlock &RestoreMBB, Register SGPR,
225 /// \returns true if this class contains only SGPR registers
230 /// \returns true if this class ID contains only SGPR registers
259 /// \returns true only if this class contains both VGPR and SGPR registers
274 /// \returns true if this class contains SGPR registers.
292 /// \returns A SGPR reg class with the same width as \p SRC
H A DSIMachineFunctionInfo.h364 // A CSR SGPR value can be preserved inside a callee using one of the following
366 // 1. Copy to an unused scratch SGPR.
370 // for an SGPR at function prolog/epilog.
535 // To track virtual VGPR + lane index for each subregister of the SGPR spilled
539 // To track physical VGPR + lane index for CSR SGPR spills and special SGPRs
570 // To track the SGPR spill method used for a CSR SGPR register during
571 // frame lowering. Even though the SGPR spills are handled during
704 // Get the scratch SGPR if allocated to save/restore \p Reg.
716 // Get all scratch SGPRs allocated to copy/restore the SGPR spills.
724 // Check if \p FI is allocated for any SGPR spill to a VGPR lane during PEI.
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H A DSIRegisterInfo.cpp33 "amdgpu-spill-sgpr-to-vgpr",
66 // - Try to scavenge SGPR(s) to save exec
85 // The SGPR to save
101 // Scavenged SGPR to save EXEC.
160 // Writes these instructions if an SGPR can be scavenged:
165 // Writes these instructions if no SGPR can be scavenged:
178 assert(RS && "Cannot spill SGPR to memory without RegScavenger"); in prepare()
229 "unhandled SGPR spill to memory"); in prepare()
244 // Writes these instructions if an SGPR can be scavenged:
249 // Writes these instructions if no SGPR can be scavenged:
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H A DAMDGPURegisterBankInfo.cpp16 /// VGPR (vector), and SGPR (scalar). Additionally the VCC register bank is a
21 /// Copying from VGPR to SGPR is generally illegal, unless the value is known to
23 /// copies as on other targets. Operations which require uniform, SGPR operands
34 /// bank. To distinguish whether an SGPR should use the SGPR or VCC register
35 /// bank, we need to know the use context type. An SGPR s1 value always means a
36 /// VCC bank value, otherwise it will be the SGPR bank. A scalar compare sets
51 /// restriction. Most VALU instructions can use SGPR operands, but may read at
52 /// most 1 SGPR or constant literal value (this to 2 in gfx10 for most
53 /// instructions). This is one unique SGPR, so the same SGPR may be used for
55 /// operands should be legal as an SGPR, but this is contextually dependent on
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H A DAMDGPUGenRegisterBankInfo.def61 {0, 1, SGPRRegBank}, // SGPR begin
176 /*32-bit sgpr*/ {&SGPROnly64BreakDown[0], 1},
177 /*2 x 32-bit sgpr*/ {&SGPROnly64BreakDown[1], 2},
178 /*64-bit sgpr */ {&SGPROnly64BreakDown[3], 1},
H A DGCNRegPressure.cpp41 return STI->isSGPRClass(RC) ? SGPR : (STI->isAGPRClass(RC) ? AGPR : VGPR); in getRegKind()
123 // SGPR excess pressure conditions in less()
129 // The number of virtual VGPRs required to handle excess SGPR in less()
136 // Unified excess pressure conditions, accounting for VGPRs used for SGPR in less()
146 // Arch VGPR excess pressure conditions, accounting for VGPRs used for SGPR in less()
173 // SGPR spills in less()
193 // of the pressures has VGPR usage from SGPR spills, prefer the pressure in less()
194 // with SGPR spills. in less()
198 // accounting for SGPR spills, prefer fewer SGPR spills. in less()
947 OS << PFX " SGPR VGPR\n"; in runOnMachineFunction()
H A DAMDGPUPassRegistry.def118 MACHINE_FUNCTION_PASS("amdgpu-wait-sgpr-hazards", AMDGPUWaitSGPRHazardsPass())
121 MACHINE_FUNCTION_PASS("si-fix-sgpr-copies", SIFixSGPRCopiesPass())
131 MACHINE_FUNCTION_PASS("si-lower-sgpr-spills", SILowerSGPRSpillsPass())
H A DAMDGPURegBankSelect.cpp11 /// Sgpr - uniform values and some lane masks
145 // lane mask(vcc) and regular sgpr S1. in reAssignRegBankOnDef()
147 // non-trivial sgpr-S1-to-vcc copy. But pre-inst-selection of si_if sets in reAssignRegBankOnDef()
149 // - the regular sgpr S1(uniform) instruction is now broken since in reAssignRegBankOnDef()
H A DGCNSubtarget.h518 /// A read of an SGPR by SMRD instruction requires 4 wait states when the SGPR
524 /// A read of an SGPR by a VMEM instruction requires 5 wait states when the
525 /// SGPR was written by a VALU Instruction.
672 // The ST addressing mode means no registers are used, either VGPR or SGPR,
1496 /// \returns SGPR allocation granularity supported by the subtarget.
1501 /// \returns SGPR encoding granularity supported by the subtarget.
1551 /// requested using "amdgpu-num-sgpr" attribute attached to function \p MF.
1561 /// requested using "amdgpu-num-sgpr" attribute attached to function \p F.
1759 // Returns the size in number of SGPRs for preload user SGPR field.
1788 // Compute directly in sgpr[0:1]
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H A DAMDGPURegBankLegalizeRules.h132 // sgpr scalars, pointers, vectors and B-types
201 // not done by legalizer since instructions is available in either sgpr or vgpr.
202 // For example S64 AND is available on sgpr, for that reason S64 AND is legal in
H A DAMDGPURegBankLegalizeHelper.cpp729 // vcc, sgpr and vgpr scalars, pointers and vectors in applyMappingDst()
758 // sgpr and vgpr B-types in applyMappingDst()
815 // sgpr trunc in applyMappingDst()
859 // sgpr scalars, pointers and vectors in applyMappingSrc()
875 // sgpr B-types in applyMappingSrc()
926 // sgpr and vgpr scalars with extend in applyMappingSrc()
1010 // with sgpr reg class and S1 LLT. in applyMappingPHI()
1019 // Uniform G_PHIs have all sgpr registers. in applyMappingPHI()
1020 // Divergent G_PHIs have vgpr dst but inputs can be sgpr or vgpr. in applyMappingPHI()
H A DSIInstrInfo.cpp199 // Allow sinking if MI edits lane mask (divergent i1 in sgpr). in isSafeToSink()
627 const char *Msg = "illegal VGPR to SGPR copy") { in reportIllegalCopy()
637 /// Handle copying from SGPR to AGPR, or from AGPR to AGPR on GFX908. It is not
654 "Source register of the copy should be either an SGPR or an AGPR."); in indirectCopyToAGPR()
775 // Is SGPR aligned? If so try to combine with next. in expandSGPRCopy()
1756 // The SGPR spill/restore instructions only work on number sgprs, so we need in storeRegToStackSlot()
3049 // As SGPR needs VGPR to be spilled, we reuse the slot of temporary VGPR for in insertIndirectBranch()
3050 // SGPR spill. in insertIndirectBranch()
3667 // can be materialized in an sgpr instead of a vgpr: in foldImmediate()
3787 // and we now have SGPR as SRC1. If so 2 inlined in foldImmediate()
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H A DAMDGPURegisterBanks.td9 def SGPRRegBank : RegisterBank<"SGPR",
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td216 // Set EXEC according to a thread count packed in an SGPR input:
222 [llvm_i32_ty, // 32-bit SGPR input
1081 [llvm_any_ty], // rsrc(SGPR); Valid types: v4i32 and v8i32
1082 !if(P_.IsSample, [llvm_any_ty, // samp(SGPR);
1331 [llvm_v4i32_ty, // rsrc(SGPR)
1360 [llvm_v4i32_ty, // rsrc(SGPR)
1362 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
1377 [llvm_v4i32_ty, // rsrc(SGPR)
1379 llvm_i32_ty, // soffset(SGPR/imm, excluded from bounds checking and swizzling)
1390 [AMDGPUBufferRsrcTy, // rsrc(SGPR)
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