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/linux/drivers/gpu/drm/xe/
H A Dxe_reg_sr.c53 * Don't allow overwriting values: clr_bits/set_bits should be disjoint in compatible_entries()
56 if (e1->clr_bits & e2->clr_bits || e1->set_bits & e2->set_bits || in compatible_entries()
57 e1->clr_bits & e2->set_bits || e1->set_bits & e2->clr_bits) in compatible_entries()
88 pentry->set_bits |= e->set_bits; in xe_reg_sr_add()
112 idx, e->clr_bits, e->set_bits, in xe_reg_sr_add()
155 * - Masked registers can't have set_bits with upper bits set in apply_one_mmio()
156 * - set_bits must be contained in clr_bits in apply_one_mmio()
158 val |= entry->set_bits; in apply_one_mmio()
210 reg, entry->clr_bits, entry->set_bits, in xe_reg_sr_dump()
241 u32 mask = entry->clr_bits | entry->set_bits; in xe_reg_sr_readback_check()
[all …]
H A Dxe_reg_whitelist.c160 .set_bits = entry->reg.addr | entry->set_bits, in whitelist_apply_to_hwe()
208 u32 val = entry->set_bits; in xe_reg_whitelist_print_entry()
H A Dxe_reg_sr_types.h17 u32 set_bits; member
H A Dxe_gt.c297 val |= entry->set_bits; in emit_wa_job()
331 *cs++ = entry->set_bits; in emit_wa_job()
348 entry->reg.addr, entry->clr_bits, entry->set_bits, in emit_wa_job()
/linux/tools/perf/bench/
H A Dfind-bit-bench.c63 unsigned int set_bits, skip; in do_for_each_set_bit() local
68 for (set_bits = 1; set_bits <= num_bits; set_bits <<= 1) { in do_for_each_set_bit()
70 skip = num_bits / set_bits; in do_for_each_set_bit()
85 assert(old + (inner_iterations * set_bits) == accumulator); in do_for_each_set_bit()
101 assert(old + (inner_iterations * set_bits) == accumulator); in do_for_each_set_bit()
108 inner_iterations, set_bits, num_bits); in do_for_each_set_bit()
/linux/drivers/net/ethernet/apm/xgene-v2/
H A Dring.c26 raw_desc->m0 = cpu_to_le64(SET_BITS(E, 1) | in xge_setup_desc()
27 SET_BITS(PKT_SIZE, SLOT_EMPTY)); in xge_setup_desc()
29 raw_desc->m1 = cpu_to_le64(SET_BITS(NEXT_DESC_ADDRL, next_dma) | in xge_setup_desc()
30 SET_BITS(NEXT_DESC_ADDRH, dma_h)); in xge_setup_desc()
H A Dmain.c96 raw_desc->m1 = cpu_to_le64(SET_BITS(NEXT_DESC_ADDRL, addr_lo) | in xge_refill_buffers()
97 SET_BITS(NEXT_DESC_ADDRH, addr_hi) | in xge_refill_buffers()
98 SET_BITS(PKT_ADDRH, in xge_refill_buffers()
102 raw_desc->m0 = cpu_to_le64(SET_BITS(PKT_ADDRL, dma_addr) | in xge_refill_buffers()
103 SET_BITS(E, 1)); in xge_refill_buffers()
203 raw_desc->m1 = cpu_to_le64(SET_BITS(NEXT_DESC_ADDRL, addr_lo) | in xge_start_xmit()
204 SET_BITS(NEXT_DESC_ADDRH, addr_hi) | in xge_start_xmit()
205 SET_BITS(PKT_ADDRH, in xge_start_xmit()
214 raw_desc->m0 = cpu_to_le64(SET_BITS(PKT_ADDRL, dma_addr) | in xge_start_xmit()
215 SET_BITS(PKT_SIZE, len) | in xge_start_xmit()
[all …]
H A Dring.h95 #define SET_BITS(field, val) \ macro
/linux/drivers/net/ethernet/amd/xgbe/
H A Dxgbe-common.h1394 #define SET_BITS(_var, _index, _width, _val) \ macro
1424 SET_BITS((_var), \
1459 SET_BITS(reg_val, \
1485 SET_BITS(reg_val, \
1509 SET_BITS(reg_val, \
1524 SET_BITS((_var), \
1549 SET_BITS((_var), \
1567 SET_BITS(reg_val, \
1587 SET_BITS(reg_val, \
1610 SET_BITS(reg_val, \
[all …]
/linux/drivers/watchdog/
H A Drc32434_wdt.c68 #define SET_BITS(addr, or, nand) \ macro
104 SET_BITS(wdt_reg->errcs, or, nand); in rc32434_wdt_start()
113 SET_BITS(wdt_reg->wtc, or, nand); in rc32434_wdt_start()
124 SET_BITS(wdt_reg->wtc, 0, 1 << RC32434_WTC_EN); in rc32434_wdt_stop()
/linux/arch/arm/mach-omap2/
H A Domap-secure.c185 * @set_bits: bits to set in ACR
190 u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits) in rx51_secure_update_aux_cr() argument
197 acr |= set_bits; in rx51_secure_update_aux_cr()
H A Domap-secure.h77 extern u32 rx51_secure_update_aux_cr(u32 set_bits, u32 clear_bits);
/linux/drivers/gpu/drm/sprd/
H A Dsprd_dpu.h75 dpu_reg_set(struct dpu_context *ctx, u32 offset, u32 set_bits) in dpu_reg_set() argument
79 writel(bits | set_bits, ctx->base + offset); in dpu_reg_set()
/linux/fs/netfs/
H A Dfscache_io.c167 bool set_bits; member
201 wreq->set_bits); in fscache_wreq_done()
233 wreq->set_bits = cond; in __fscache_write_to_cache()
/linux/include/trace/events/
H A Dbtrfs.h2083 u64 start, u64 len, unsigned set_bits),
2085 TP_ARGS(tree, start, len, set_bits),
2093 __field( unsigned, set_bits)
2104 __entry->set_bits = set_bits;
2108 "io_tree=%s ino=%llu root=%llu start=%llu len=%llu set_bits=%s",
2111 __print_flags(__entry->set_bits, "|", EXTENT_FLAGS))
2149 u64 start, u64 len, unsigned set_bits, unsigned clear_bits),
2151 TP_ARGS(tree, start, len, set_bits, clear_bits),
2159 __field( unsigned, set_bits)
2171 __entry->set_bits = set_bits;
[all …]
/linux/drivers/hwmon/
H A Dgl518sm.c299 #define set_bits(type, suffix, value, reg, mask, shift) \ macro
322 set_bits(type, suffix, value, reg, 0x00ff, 0)
324 set_bits(type, suffix, value, reg, 0xff00, 8)
328 set_bits(BOOL, fan_auto1, fan_auto1, GL518_REG_MISC, 0x08, 3);
337 set_bits(BOOL, beep_enable, beep_enable, GL518_REG_CONF, 0x04, 2);
/linux/drivers/tty/serial/
H A Dsunzilog.c646 unsigned char set_bits, clear_bits; in sunzilog_set_mctrl() local
648 set_bits = clear_bits = 0; in sunzilog_set_mctrl()
651 set_bits |= RTS; in sunzilog_set_mctrl()
655 set_bits |= DTR; in sunzilog_set_mctrl()
660 up->curregs[R5] |= set_bits; in sunzilog_set_mctrl()
756 unsigned char set_bits, clear_bits, new_reg; in sunzilog_break_ctl() local
759 set_bits = clear_bits = 0; in sunzilog_break_ctl()
762 set_bits |= SND_BRK; in sunzilog_break_ctl()
768 new_reg = (up->curregs[R5] | set_bits) & ~clear_bits; in sunzilog_break_ctl()
H A Dpmac_zilog.c516 unsigned char set_bits, clear_bits; in pmz_set_mctrl() local
525 set_bits = clear_bits = 0; in pmz_set_mctrl()
529 set_bits |= RTS; in pmz_set_mctrl()
534 set_bits |= DTR; in pmz_set_mctrl()
539 uap->curregs[R5] |= set_bits; in pmz_set_mctrl()
544 set_bits, clear_bits, uap->curregs[R5]); in pmz_set_mctrl()
664 unsigned char set_bits, clear_bits, new_reg; in pmz_break_ctl() local
667 set_bits = clear_bits = 0; in pmz_break_ctl()
670 set_bits |= SND_BRK; in pmz_break_ctl()
676 new_reg = (uap->curregs[R5] | set_bits) & ~clear_bits; in pmz_break_ctl()
/linux/drivers/gpio/
H A Dgpio-thunderx.c279 u64 set_bits, clear_bits; in thunderx_gpio_set_multiple() local
283 set_bits = bits[bank] & mask[bank]; in thunderx_gpio_set_multiple()
285 writeq(set_bits, txgpio->register_base + (bank * GPIO_2ND_BANK) + GPIO_TX_SET); in thunderx_gpio_set_multiple()
/linux/arch/powerpc/include/asm/
H A Dbitops.h82 DEFINE_BITOP(set_bits, or, "")
131 set_bits(BIT_MASK(nr), addr + BIT_WORD(nr)); in DEFINE_CLROP()
/linux/drivers/net/ethernet/chelsio/cxgb3/
H A Dael1002.c81 unsigned short set_bits; member
91 rv->set_bits); in set_phy_regs()
95 rv->set_bits); in set_phy_regs()
/linux/drivers/media/radio/si4713/
H A Dsi4713.c76 #define set_bits(p, v, b, m) (((p) & ~(m)) | ((v) << (b))) macro
1203 val = set_bits(val, ctrl->val, bit, mask); in si4713_s_ctrl()
1330 p = set_bits(p, stereo, 1, 1 << 1); in si4713_s_modulator()
1331 p = set_bits(p, rds, 2, 1 << 2); in si4713_s_modulator()
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192du/
H A Dhw.c20 u8 set_bits, u8 clear_bits) in _rtl92du_set_bcn_ctrl_reg() argument
25 rtlusb->reg_bcn_ctrl_val |= set_bits; in _rtl92du_set_bcn_ctrl_reg()
/linux/drivers/ntb/hw/idt/
H A Dntb_hw_idt.c404 * @set_bits: Bitmask to set
416 u64 valid_mask, u64 set_bits) in idt_reg_set_bits() argument
421 if (set_bits & ~(u64)valid_mask) in idt_reg_set_bits()
426 data = idt_nt_read(ndev, reg) | (u32)set_bits; in idt_reg_set_bits()
439 * @set_bits: Bitmask to clear
/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
H A Dhw.c47 u8 set_bits, u8 clear_bits) in _rtl92de_set_bcn_ctrl_reg() argument
52 rtlpci->reg_bcn_ctrl_val |= set_bits; in _rtl92de_set_bcn_ctrl_reg()

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