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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v4_4.c34 /* helper function that allow only use sdma0 register offset
60 { "SDMA_MBANK_DATA_BUF0_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
64 { "SDMA_MBANK_DATA_BUF1_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
68 { "SDMA_MBANK_DATA_BUF2_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
72 { "SDMA_MBANK_DATA_BUF3_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
76 { "SDMA_MBANK_DATA_BUF4_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
80 { "SDMA_MBANK_DATA_BUF5_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
84 { "SDMA_MBANK_DATA_BUF6_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
88 { "SDMA_MBANK_DATA_BUF7_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
92 { "SDMA_MBANK_DATA_BUF8_SED", SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_EDC_COUNTER),
[all …]
H A Dsdma_v4_0.c33 #include "sdma0/sdma0_4_2_offset.h"
34 #include "sdma0/sdma0_4_2_sh_mask.h"
49 #include "sdma0/sdma0_4_1_default.h"
55 #include "ivsrcid/sdma0/irqsrcs_sdma0_4_0.h"
136 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CHICKEN_BITS, 0xfe931f07, 0x02831d07),
137 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_CLK_CTRL, 0xff000ff0, 0x3f000100),
138 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_IB_CNTL, 0x800f0100, 0x00000100),
139 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_GFX_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
140 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_IB_CNTL, 0x800f0100, 0x00000100),
141 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_PAGE_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
[all …]
H A Damdgpu_amdkfd_arcturus.c29 #include "sdma0/sdma0_4_2_2_offset.h"
30 #include "sdma0/sdma0_4_2_2_sh_mask.h"
81 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
H A Dgmc_v9_0.c107 [27][0] = "SDMA0",
119 [27][1] = "SDMA0",
131 [27][0] = "SDMA0",
144 [27][1] = "SDMA0",
163 [32+14][0] = "SDMA0",
171 [15][1] = "SDMA0",
195 [32+15][0] = "SDMA0",
203 [15][1] = "SDMA0",
223 [15][0] = "SDMA0",
241 [15][1] = "SDMA0",
[all …]
H A Damdgpu_amdkfd_gfx_v10_3.c143 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
147 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
151 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
155 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
H A Dsdma_v7_1.c120 u32 dev_inst = GET_INST(SDMA0, instance); in sdma_v7_1_get_reg_offset()
663 * Loads the sDMA0/1 ucode.
1326 xcc_id, GET_INST(SDMA0, i) % adev->sdma.num_inst_per_xcc, in sdma_v7_1_sw_init()
1334 GET_INST(SDMA0, i) % adev->sdma.num_inst_per_xcc); in sdma_v7_1_sw_init()
1540 if (inst == GET_INST(SDMA0, instances)) in sdma_v7_1_process_trap_irq()
1691 dev_inst = GET_INST(SDMA0, i); in sdma_v7_1_set_ring_funcs()
H A Damdgpu_amdkfd_gc_9_4_3.c48 SOC15_REG_OFFSET(SDMA0, GET_INST(SDMA0, engine_id), in get_sdma_rlc_reg_offset()
H A Damdgpu_amdkfd_gfx_v9.c27 #include "sdma0/sdma0_4_0_offset.h"
28 #include "sdma0/sdma0_4_0_sh_mask.h"
194 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
H A Damdgpu_amdkfd_gfx_v12.c85 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
H A Dsdma_v7_0.c675 * Loads the sDMA0/1 ucode.
1481 u32 sdma0, sdma1; in sdma_v7_0_wait_for_idle() local
1485 sdma0 = RREG32(sdma_v7_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); in sdma_v7_0_wait_for_idle()
1488 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) in sdma_v7_0_wait_for_idle()
H A Dsdma_v6_0.c662 * Loads the sDMA0/1 ucode.
1526 u32 sdma0, sdma1; in sdma_v6_0_wait_for_idle() local
1530 sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); in sdma_v6_0_wait_for_idle()
1533 if (sdma0 & sdma1 & SDMA0_STATUS_REG__IDLE_MASK) in sdma_v6_0_wait_for_idle()
H A Damdgpu_amdkfd_gfx_v10.c165 SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
168 * on SDMA1 base address (dw 0x1860) but based on SDMA0 in get_sdma_rlc_reg_offset()
H A Dcik_ih.c241 * INSTANCE_ID - 0 = sdma0, 1 = sdma1
H A Dgfxhub_v2_0.c48 "SDMA0",
H A Dgfxhub_v3_0_3.c50 "SDMA0",
H A Dgfxhub_v11_5_0.c52 "SDMA0",
H A Dgfxhub_v3_0.c47 "SDMA0",
H A Dgfxhub_v12_0.c51 "SDMA0",
H A Damdgpu_irq.c76 "SDMA0",
H A Dpsp_v11_0.c38 #include "sdma0/sdma0_4_0_offset.h"
H A Damdgpu_amdkfd_gfx_v11.c134 sdma_engine_reg_base = SOC15_REG_OFFSET(SDMA0, 0, in get_sdma_rlc_reg_offset()
H A Damdgpu_dev_coredump.c48 [SDMA0_HWIP] = "SDMA0",
H A Dsoc21.c294 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
/linux/drivers/gpu/drm/radeon/
H A Dcik_sdma.c41 * and gfx. There are two DMA engines (SDMA0, SDMA1)
177 ref_and_mask = SDMA0; in cik_sdma_hdp_flush_ring_emit()
458 * Loads the sDMA0/1 ucode.
479 /* sdma0 */ in cik_sdma_load_microcode()
499 /* sdma0 */ in cik_sdma_load_microcode()
/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_mqd_manager_v9.c33 #include "sdma0/sdma0_4_0_sh_mask.h"

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