| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | cdns,sdhci.yaml | 94 cdns,phy-dll-delay-sdclk:
96 Value of the delay introduced on the sdclk output for all modes except
102 cdns,phy-dll-delay-sdclk-hsmmc:
104 Value of the delay introduced on the sdclk output for HS200, HS400 and
157 cdns,phy-dll-delay-sdclk = <0>;
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| H A D | marvell,xenon-sdhci.yaml | 213 clocks = <&sdclk 0>, <&axi_clk 0>;
255 clocks = <&sdclk 0>;
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| /linux/drivers/mmc/host/ |
| H A D | sdhci-xenon-phy.c | 238 * 1. SDCLK frequency changes.
239 * 2. SDCLK is stopped and re-enabled.
490 * 2. SDCLK is higher than 52MHz in xenon_emmc_phy_strobe_delay_adj()
512 * If eMMC PHY Slow Mode is required in lower speed mode (SDCLK < 55MHz)
805 * PHY setting should be adjusted when SDCLK frequency, Bus Width
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| H A D | sdhci-of-aspeed.c | 261 * period of SDCLK = period of SDMCLK. in aspeed_sdhci_set_clock()
264 * period of SDCLK = period of SDMCLK * 2 * (EMMC12C[7:6], EMMC[15:8]) in aspeed_sdhci_set_clock()
538 dev_err(&pdev->dev, "Unable to enable SDCLK\n"); in aspeed_sdc_probe()
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| H A D | sdhci-cadence.c | 98 { "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
99 { "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
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| H A D | sdhci-xenon.c | 53 /* Set SDCLK-off-while-idle */
491 /* Disable SDCLK-Off-While-Idle before card init */ in xenon_sdhc_prepare()
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| H A D | sdhci-s3c.c | 626 /* HSMMC on Samsung SoCs uses SDCLK as timeout clock */ in sdhci_s3c_probe()
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| H A D | uniphier-sd.c | 25 #define UNIPHIER_SD_CLKCTL_OFFEN BIT(9) // auto SDCLK stop
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| H A D | sdhci-tegra.c | 1724 * timeout clock and SW can choose TMCLK or SDCLK for hardware in sdhci_tegra_probe()
1731 * be achieved is 11s better than using SDCLK for data timeout. in sdhci_tegra_probe()
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| H A D | sdhci.h | 480 /* Controller uses SDCLK instead of TMCLK for data timeouts */
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| /linux/drivers/cpufreq/ |
| H A D | sa1110-cpufreq.c | 152 * If SDCLK would invalidate the SDRAM timings, in sdram_calculate_timing()
153 * run SDCLK at half speed. in sdram_calculate_timing()
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| /linux/arch/arm64/boot/dts/socionext/ |
| H A D | uniphier-ld11.dtsi | 464 cdns,phy-dll-delay-sdclk = <21>;
465 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
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| H A D | uniphier-pxs3.dtsi | 422 cdns,phy-dll-delay-sdclk = <21>;
423 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
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| H A D | uniphier-ld20.dtsi | 602 cdns,phy-dll-delay-sdclk = <21>;
603 cdns,phy-dll-delay-sdclk-hsmmc = <21>;
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| /linux/drivers/pinctrl/uniphier/ |
| H A D | pinctrl-uniphier-nx1.c | 18 UNIPHIER_PINCTRL_PIN(1, "SDCLK", UNIPHIER_PIN_IECTRL_EXIST,
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| H A D | pinctrl-uniphier-sld8.c | 111 UNIPHIER_PINCTRL_PIN(32, "SDCLK", 8,
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| H A D | pinctrl-uniphier-ld4.c | 147 UNIPHIER_PINCTRL_PIN(44, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
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| H A D | pinctrl-uniphier-ld6b.c | 156 UNIPHIER_PINCTRL_PIN(47, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
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| H A D | pinctrl-uniphier-pro5.c | 765 UNIPHIER_PINCTRL_PIN(250, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
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| H A D | pinctrl-uniphier-pxs2.c | 156 UNIPHIER_PINCTRL_PIN(47, "SDCLK", UNIPHIER_PIN_IECTRL_NONE,
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| H A D | pinctrl-uniphier-pxs3.c | 144 UNIPHIER_PINCTRL_PIN(43, "SDCLK", UNIPHIER_PIN_IECTRL_EXIST,
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| /linux/drivers/pinctrl/ |
| H A D | pinctrl-ep93xx.c | 129 PINCTRL_PIN(10, "SDCLK"),
437 PINCTRL_PIN(53, "SDCLK"), /* D3 */
858 PINCTRL_PIN(117, "SDCLK"), /* G4 */
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| /linux/drivers/clk/ |
| H A D | clk-aspeed.c | 71 [ASPEED_CLK_GATE_SDCLK] = { 27, 16, "sdclk-gate", NULL, 0 }, /* SDIO/SD */
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| /linux/arch/m68k/include/asm/ |
| H A D | MC68VZ328.h | 591 #define PM_SDCLK 0x01 /* Use SDCLK as PM[0] */
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| /linux/drivers/comedi/drivers/ |
| H A D | ni_mio_common.c | 3842 * Assert SDCLK (active low, inverted), wait for half of in ni_serial_sw_readwrite8()
3843 * the delay, deassert SDCLK, and wait for the other half. in ni_serial_sw_readwrite8()
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