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/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Dnau8824.txt6 - compatible : Must be "nuvoton,nau8824"
8 - reg : the I2C address of the device. This is either 0x1a (CSB=0) or 0x1b (CSB=1).
11 - nuvoton,jkdet-polarity: JKDET pin polarity. 0 - active high, 1 - active low.
13 - nuvoton,vref-impedance: VREF Impedance selection
14 0 - Open
15 1 - 25 kOhm
16 2 - 125 kOhm
17 3 - 2.5 kOhm
19 - nuvoton,micbias-voltage: Micbias voltage level.
20 0 - VDDA
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H A Dnau8825.txt6 - compatible : Must be "nuvoton,nau8825"
8 - reg : the I2C address of the device. This is either 0x1a (CSB=0) or 0x1b (CSB=1).
11 - nuvoton,jkdet-enable: Enable jack detection via JKDET pin.
12 - nuvoton,jkdet-pull-enable: Enable JKDET pin pull. If set - pin pull enabled,
14 - nuvoton,jkdet-pull-up: Pull-up JKDET pin. If set then JKDET pin is pull up, otherwise pull down.
15 - nuvoton,jkdet-polarity: JKDET pin polarity. 0 - active high, 1 - active low.
17 - nuvoton,vref-impedance: VREF Impedance selection
18 0 - Open
19 1 - 25 kOhm
20 2 - 125 kOhm
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H A Dnuvoton,nau8824.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Hsu <KCHSU0@nuvoton.com>
13 - $ref: dai-common.yaml#
18 - nuvoton,nau8824
23 '#sound-dai-cells':
28 - description: The phandle of the master clock to the CODEC
30 clock-names:
32 - const: mclk
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H A Dnuvoton,nau8825.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - John Hsu <KCHSU0@nuvoton.com>
13 - $ref: dai-common.yaml#
18 - nuvoton,nau8825
26 nuvoton,jkdet-enable:
31 nuvoton,jkdet-pull-enable:
34 If set - pin pull enabled, otherwise pin in high impedance state.
37 nuvoton,jkdet-pull-up:
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/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra210-smaug.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/mfd/max77620.h>
6 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
12 compatible = "google,smaug-rev8", "google,smaug-rev7",
13 "google,smaug-rev6", "google,smaug-rev5",
14 "google,smaug-rev4", "google,smaug-rev3",
15 "google,smaug-rev2", "google,smaug-rev1",
25 stdout-path = "serial0:115200n8";
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/freebsd/contrib/wpa/src/common/
H A Dqca-vendor.h3 * Copyright (c) 2014-2017, Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2020, The Linux Foundation
5 * Copyright (c) 2021-2023, Qualcomm Innovation Center, Inc.
28 * enum qca_radiotap_vendor_ids - QCA radiotap vendor namespace IDs
41 * Global NSS configuration - Applies to all bands (2.4 GHz and 5/6 GHz)
62 * Per band NSS configuration - Applies to the 2.4 GHz or 5/6 GHz band
79 * Global chain configuration - Applies to all bands (2.4 GHz and 5/6 GHz)
96 * Per band chain configuration - Applies to the 2.4 GHz or 5/6 GHz band
117 * Case 1: CONFIG_NSS + CONFIG_TX_NSS/RX_NSS - Only CONFIG_NSS is applied
120 * Case 2: CONFIG_NSS + CONFIG_TX_NSS + CONFIG_RX_NSS - Same NSS values are
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/freebsd/sys/contrib/dev/rtw89/
H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
54 #define RTW89_RSSI_RAW_TO_DBM(rssi) ((s8)((rssi) >> RSSI_FACTOR) - MAX_RSSI)
111 RTW89_CH_6G_BAND_IDX6, /* Ultra-high */
112 RTW89_CH_6G_BAND_IDX7, /* Ultra-high */
271 * RTW89_ADDR_CAM_SEC_ALL_UNI : 0 - 6 unicast
272 * RTW89_ADDR_CAM_SEC_NORMAL : 0 - 1 unicast, 2 - 4 group, 5 - 6 BIP
273 * RTW89_ADDR_CAM_SEC_4GROUP : 0 - 1 unicast, 2 - 5 group, 6 BIP
771 #define RTW89_MIN_VALID_POWER_CONSTRAINT (-10) /* unit: dBm */
977 /* The follow-up are derived from the above. We must ensure that it
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H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
14 #include "sar.h"
20 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def; in rtw89_phy0_phy1_offset()
22 return phy->phy0_phy1_offset(rtwdev, addr); in rtw89_phy0_phy1_offset()
28 u32 bit_rate = report->bit_rate; in get_max_amsdu_len()
35 if (report->might_fallback_legacy) in get_max_amsdu_len()
50 return rtwdev->chip->max_amsdu_limit; in get_max_amsdu_len()
66 ra_mask |= GENMASK_ULL(highest_mcs - gap, 0) << nss; in get_mcs_ra_mask()
69 ra_mask |= GENMASK_ULL(highest_mcs - gap * 2, 0) << nss; in get_mcs_ra_mask()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DLoopStrengthReduce.cpp1 //===- LoopStrengthReduce.cpp - Strength Reduce IVs in Loops --------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
15 // rewrites expressions to take advantage of scaled-index addressing modes
19 // Terminology note: this code has a lot of handling for "post-increment" or
20 // "post-inc" users. This is not talking about post-increment addressing modes;
31 // example, the icmp is a post-increment user, since it uses %i.next, which is
33 // case of post-increment users is users outside the loop.
37 // TODO: Handle multiple loops at a time.
47 // we may not actually need both reg and (-1 * reg) in registers; the
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZScheduleZEC12.td1 //=- SystemZScheduleZEC12.td - SystemZ Scheduling Definitions --*- tblgen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
67 foreach L = 1-30 in {
86 foreach Num = 2-6 in { let ReleaseAtCycles = [Num] in {
100 // -------------------------- INSTRUCTIONS ---------------------------------- //
108 //===----------------------------------------------------------------------===//
110 //===----------------------------------------------------------------------===//
112 // Pseudo -> LA / LAY
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H A DSystemZScheduleZ196.td1 //=- SystemZScheduleZ196.td - SystemZ Scheduling Definitions ---*- tblgen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
67 foreach L = 1-30 in {
85 foreach Num = 2-6 in { let ReleaseAtCycles = [Num] in {
97 // -------------------------- INSTRUCTIONS ---------------------------------- //
105 //===----------------------------------------------------------------------===//
107 //===----------------------------------------------------------------------===//
109 def : InstRW<[WLat1, FXU, NormalGr], (instregex "ADJDYNALLOC$")>; // Pseudo -> LA / LAY
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H A DSystemZScheduleZ15.td1 //-- SystemZScheduleZ15.td - SystemZ Scheduling Definitions ----*- tblgen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
71 foreach L = 1-30 in
95 foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
116 // -------------------------- INSTRUCTIONS ---------------------------------- //
124 //===----------------------------------------------------------------------===//
126 //===----------------------------------------------------------------------===//
128 // Pseudo -> LA / LAY
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H A DSystemZScheduleZ14.td1 //-- SystemZScheduleZ14.td - SystemZ Scheduling Definitions ----*- tblgen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
71 foreach L = 1-30 in
95 foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
116 // -------------------------- INSTRUCTIONS ---------------------------------- //
124 //===----------------------------------------------------------------------===//
126 //===----------------------------------------------------------------------===//
128 // Pseudo -> LA / LAY
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H A DSystemZScheduleZ13.td1 //-- SystemZScheduleZ13.td - SystemZ Scheduling Definitions ----*- tblgen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
71 foreach L = 1-30 in
95 foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
116 // -------------------------- INSTRUCTIONS ---------------------------------- //
124 //===----------------------------------------------------------------------===//
126 //===----------------------------------------------------------------------===//
128 // Pseudo -> LA / LAY
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H A DSystemZScheduleZ16.td1 //-- SystemZScheduleZ16.td - SystemZ Scheduling Definitions ----*- tblgen -*-=//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
71 foreach L = 1-30 in
95 foreach Num = 2-5 in { let ReleaseAtCycles = [Num] in {
117 // -------------------------- INSTRUCTIONS ---------------------------------- //
125 //===----------------------------------------------------------------------===//
127 //===----------------------------------------------------------------------===//
129 // Pseudo -> LA / LAY
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/
H A DLoopVectorize.cpp1 //===- LoopVectorize.cpp - A Loop Vectorizer ------------------------------===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 // and generates target-independent LLVM-IR.
20 // 2. LoopVectorizationLegality - A unit that checks for the legality
22 // 3. InnerLoopVectorizer - A unit that performs the actual
24 // 4. LoopVectorizationCostModel - A unit that checks for the profitability
31 // http://lists.llvm.org/pipermail/llvm-dev/2017-December/119523.html). For this
32 // purpose, we temporarily introduced the VPlan-native vectorization path: an
36 //===----------------------------------------------------------------------===//
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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrCompiler.td1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
19 return getI32Imm((uint32_t)N->getZExtValue(), SDLoc(N));
23 //===----------------------------------------------------------------------===//
36 // pointer before prolog-epilog rewriting occurs.
54 // pointer before prolog-epilog rewriting occurs.
71 // x86-64 va_start lowering magic.
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/freebsd/share/dict/
H A Dweb240250 compare
99810 Jean-Christophe
99811 Jean-Pierre
173628 sar
203545 time