Searched +full:rk3568 +full:- +full:pipe +full:- +full:grf (Results 1 – 11 of 11) sorted by relevance
/linux/Documentation/devicetree/bindings/phy/ |
H A D | phy-rockchip-naneng-combphy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Heiko Stuebner <heiko@sntech.de> 15 - rockchip,rk3562-naneng-combphy 16 - rockchip,rk3568-naneng-combphy 17 - rockchip,rk3576-naneng-combphy 18 - rockchip,rk3588-naneng-combphy 25 - description: reference clock [all …]
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H A D | rockchip,pcie3-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Heiko Stuebner <heiko@sntech.de> 15 - rockchip,rk3568-pcie3-phy 16 - rockchip,rk3588-pcie3-phy 25 clock-names: 29 data-lanes: 32 (controller-number +1 ) [all …]
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/linux/Documentation/devicetree/bindings/soc/rockchip/ |
H A D | grf.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/soc/rockchip/grf.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Rockchip General Register Files (GRF) 10 - Heiko Stuebner <heiko@sntech.de> 15 - items: 16 - enum: 17 - rockchip,rk3288-sgrf 18 - rockchip,rk3528-ioc-grf [all …]
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/linux/arch/arm64/boot/dts/rockchip/ |
H A D | rk3568.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include "rk356x-base.dtsi" 9 compatible = "rockchip,rk3568"; 11 cpu0_opp_table: opp-table-0 { 12 compatible = "operating-points-v2"; 13 opp-shared; 15 opp-408000000 { 16 opp-hz = /bits/ 64 <408000000>; 17 opp-microvolt = <850000 850000 1150000>; 18 clock-latency-ns = <40000>; [all …]
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H A D | rk356x-base.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/rk3568-cru.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/interrupt-controller/irq.h> 9 #include <dt-bindings/phy/phy.h> 10 #include <dt-bindings/pinctrl/rockchip.h> 11 #include <dt-bindings/power/rk3568-power.h> 12 #include <dt-bindings/soc/rockchip,boot-mode.h> 13 #include <dt-bindings/thermal/thermal.h> 16 interrupt-parent = <&gic>; [all …]
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H A D | rk3588-extra.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include "rk3588-base.dtsi" 7 #include "rk3588-extra-pinctrl.dtsi" 10 hdmi1_sound: hdmi1-sound { 11 compatible = "simple-audio-card"; 12 simple-audio-card,format = "i2s"; 13 simple-audio-card,mclk-fs = <128>; 14 simple-audio-card,name = "hdmi1"; 17 simple-audio-card,codec { 18 sound-dai = <&hdmi1>; [all …]
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H A D | rk3588-base.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/rockchip,rk3588-cru.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/interrupt-controller/irq.h> 9 #include <dt-bindings/phy/phy.h> 10 #include <dt-bindings/power/rk3588-power.h> 11 #include <dt-bindings/reset/rockchip,rk3588-cru.h> 12 #include <dt-bindings/phy/phy.h> 13 #include <dt-bindings/ata/ahci.h> 14 #include <dt-bindings/thermal/thermal.h> [all …]
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H A D | rk3576.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/rockchip,rk3576-cru.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/interrupt-controller/irq.h> 9 #include <dt-bindings/phy/phy.h> 10 #include <dt-bindings/pinctrl/rockchip.h> 11 #include <dt-bindings/power/rockchip,rk3576-power.h> 12 #include <dt-bindings/reset/rockchip,rk3576-cru.h> 13 #include <dt-bindings/soc/rockchip,boot-mode.h> 18 interrupt-parent = <&gic>; [all …]
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H A D | rk3562.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/clock/rockchip,rk3562-cru.h> 7 #include <dt-bindings/interrupt-controller/arm-gic.h> 8 #include <dt-bindings/interrupt-controller/irq.h> 9 #include <dt-bindings/phy/phy.h> 10 #include <dt-bindings/power/rockchip,rk3562-power.h> 11 #include <dt-bindings/pinctrl/rockchip.h> 12 #include <dt-bindings/reset/rockchip,rk3562-cru.h> 13 #include <dt-bindings/soc/rockchip,boot-mode.h> 14 #include <dt-bindings/thermal/thermal.h> [all …]
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/linux/Documentation/devicetree/bindings/usb/ |
H A D | rockchip,dwc3.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Heiko Stuebner <heiko@sntech.de> 18 Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml 20 Type-C PHY 21 Documentation/devicetree/bindings/phy/rockchip,rk3399-typec-phy.yaml 28 - rockchip,rk3328-dwc3 29 - rockchip,rk3562-dwc3 30 - rockchip,rk3568-dwc3 [all …]
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/linux/drivers/phy/rockchip/ |
H A D | phy-rockchip-naneng-combphy.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver 8 #include <dt-bindings/phy/phy.h> 171 temp = readl(priv->mmio + reg); in rockchip_combphy_updatel() 173 writel(temp, priv->mmio + reg); in rockchip_combphy_updatel() 181 tmp = en ? reg->enable : reg->disable; in rockchip_combphy_param_write() 182 mask = GENMASK(reg->bitend, reg->bitstart); in rockchip_combphy_param_write() 183 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); in rockchip_combphy_param_write() 185 return regmap_write(base, reg->offset, val); in rockchip_combphy_param_write() 190 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; in rockchip_combphy_is_ready() [all …]
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