| /linux/include/linux/ |
| H A D | clk-provider.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
9 #include <dt-bindings/clock/clock.h>
17 * top-level framework. Custom flags for dealing with hardware specifics
20 * * CLK_SET_RATE_GATE - must be gated across rate change
21 * * CLK_SET_PARENT_GATE - must be gated across re-parent
22 * * CLK_SET_RATE_PARENT - propagate rate change up one level
23 * * CLK_IGNORE_UNUSED - do not gate even if unused
24 * * CLK_GET_RATE_NOCACHE - do not use the cached clk rate
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| /linux/include/media/ |
| H A D | v4l2-cci.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * MIPI Camera Control Interface (CCI) register access helpers.
18 * struct cci_reg_sequence - An individual write from a sequence of CCI writes
20 * @reg: Register address, use CCI_REG#() macros to encode reg width
21 * @val: Register value
23 * Register/value pairs for sequences of writes.
31 * Macros to define register address with the register width encoded
38 * Private CCI register flags, for the use of drivers.
59 * cci_read() - Read a value from a single CCI register
61 * @map: Register map to read from
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| /linux/drivers/dma/ |
| H A D | fsldma.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
108 u32 mr; /* 0x00 - Mode Register */
109 u32 sr; /* 0x04 - Status Register */
110 u64 cdar; /* 0x08 - Current descriptor address register */
111 u64 sar; /* 0x10 - Source Address Register */
112 u64 dar; /* 0x18 - Destination Address Register */
113 u32 bcr; /* 0x20 - Byte Count Register */
114 u64 ndar; /* 0x24 - Next Descriptor Address Register */
121 void __iomem *regs; /* DGSR register base */
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| /linux/include/video/ |
| H A D | s1d13xxxfb.h | 4 * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
20 /* S1DREG_REV_CODE register = prod_id (6 bits) + revision (2 bits) */
25 /* register definitions (tested on s1d13896) */
26 #define S1DREG_REV_CODE 0x0000 /* Prod + Rev Code Register */
27 #define S1DREG_MISC 0x0001 /* Miscellaneous Register */
28 #define S1DREG_GPIO_CNF0 0x0004 /* General IO Pins Configuration Register 0 */
29 #define S1DREG_GPIO_CNF1 0x0005 /* General IO Pins Configuration Register 1 */
30 #define S1DREG_GPIO_CTL0 0x0008 /* General IO Pins Control Register 0 */
31 #define S1DREG_GPIO_CTL1 0x0009 /* General IO Pins Control Register 1 */
32 #define S1DREG_CNF_STATUS 0x000C /* Configuration Status Readback Register */
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| /linux/drivers/media/platform/xilinx/ |
| H A D | xilinx-vip.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2015 Ideas on Board
6 * Copyright (C) 2013-2015 Xilinx, Inc.
18 #include <dt-bindings/media/xilinx-vip.h>
20 #include "xilinx-vip.h"
22 /* -----------------------------------------------------------------------------
48 * xvip_get_format_by_code - Retrieve format information for a media bus code
62 if (format->code == code) in xvip_get_format_by_code()
66 return ERR_PTR(-EINVAL); in xvip_get_format_by_code()
71 * xvip_get_format_by_fourcc - Retrieve format information for a 4CC
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| /linux/sound/soc/fsl/ |
| H A D | lpc3xxx-i2s.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
19 struct mutex lock; /* To serialize user-space access */
30 /* I2S controller register offsets */
42 /* i2s_daO i2s_dai register definitions */
43 #define LPC3XXX_I2S_WW8 FIELD_PREP(0x3, 0) /* Word width is 8bit */
44 #define LPC3XXX_I2S_WW16 FIELD_PREP(0x3, 1) /* Word width is 16bit */
45 #define LPC3XXX_I2S_WW32 FIELD_PREP(0x3, 3) /* Word width is 32bit */
50 #define LPC3XXX_I2S_WS_HP(s) FIELD_PREP(0x7FC0, s) /* Word select half period - 1 */
53 #define LPC3XXX_I2S_WW32_HP 0x1f /* Word select half period for 32bit word width */
54 #define LPC3XXX_I2S_WW16_HP 0x0f /* Word select half period for 16bit word width */
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| /linux/drivers/clk/hisilicon/ |
| H A D | clkdivider-hi6220.c | 1 // SPDX-License-Identifier: GPL-2.0-only
11 #include <linux/clk-provider.h>
19 #define div_mask(width) ((1 << (width)) - 1) argument
22 * struct hi6220_clk_divider - divider clock for hi6220
24 * @hw: handle between common and hardware-specific interfaces
25 * @reg: register containing divider
27 * @width: width of the divider bit field
29 * @lock: register lock
36 u8 width; member
51 val = readl_relaxed(dclk->reg) >> dclk->shift; in hi6220_clkdiv_recalc_rate()
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| /linux/Documentation/devicetree/bindings/regulator/ |
| H A D | anatop-regulator.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/regulator/anatop-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
13 - $ref: regulator.yaml#
17 const: fsl,anatop-regulator
19 regulator-name: true
21 anatop-reg-offset:
23 description: u32 value representing the anatop MFD register offset.
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| /linux/arch/arm/mach-sa1100/ |
| H A D | jornada720.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-sa1100/jornada720.c
17 #include <linux/platform_data/sa11x0-serial.h>
26 #include <asm/mach-types.h>
56 {0x0001,0x00}, // Miscellaneous Register
57 {0x01FC,0x00}, // Display Mode Register
58 {0x0004,0x00}, // General IO Pins Configuration Register 0
59 {0x0005,0x00}, // General IO Pins Configuration Register 1
60 {0x0008,0x00}, // General IO Pins Control Register 0
61 {0x0009,0x00}, // General IO Pins Control Register 1
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| /linux/drivers/edac/ |
| H A D | altera_edac.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) 2017-2018, Intel Corporation
10 #include <linux/arm-smccc.h>
14 /* SDRAM Controller CtrlCfg Register */
17 /* SDRAM Controller CtrlCfg Register Bit Masks */
25 /* SDRAM Controller Address Width Register */
28 /* SDRAM Controller Address Widths Field Register */
38 /* SDRAM Controller Interface Data Width Register */
41 /* SDRAM Controller Interface Data Width Defines */
45 /* SDRAM Controller DRAM Status Register */
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| H A D | synopsys_edac.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (C) 2012 - 2014 Xilinx, Inc.
37 /* ECC control register */
39 /* ECC log register */
41 /* ECC address register */
43 /* ECC data[31:0] register */
54 /* Control register bit field definitions */
61 /* ZQ register bit field definitions */
64 /* ECC control register bit field definitions */
68 /* ECC correctable/uncorrectable error log register definitions */
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| /linux/arch/m68k/include/asm/ |
| H A D | MC68328.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68328.h: '328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
26 * 0xFFFFF0xx -- System Control
31 * System Control Register (SCR)
36 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
39 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
42 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
45 * Mask Revision Register
52 * 0xFFFFF1xx -- Chip-Select logic
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| H A D | MC68EZ328.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68EZ328.h: 'EZ328 control registers
8 * Based on include/asm-m68knommu/MC68332.h
27 * 0xFFFFF0xx -- System Control
32 * System Control Register (SCR)
37 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
40 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
43 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
46 * Silicon ID Register (Mask Revision Register (MRR) for '328 Compatibility)
53 * 0xFFFFF1xx -- Chip-Select logic
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| H A D | MC68VZ328.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 /* include/asm-m68knommu/MC68VZ328.h: 'VZ328 control registers
5 * Copyright (c) 2000-2001 Lineo Inc. <www.lineo.com>
6 * Copyright (c) 2000-2001 Lineo Canada Corp. <www.lineo.ca>
9 * Based on include/asm-m68knommu/MC68332.h
29 * 0xFFFFF0xx -- System Control
34 * System Control Register (SCR)
39 #define SCR_WDTH8 0x01 /* 8-Bit Width Select */
42 #define SCR_BETEN 0x10 /* Bus-Error Time-Out Enable */
45 #define SCR_BETO 0x80 /* Bus-Error TimeOut */
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| /linux/drivers/clk/bcm/ |
| H A D | clk-kona.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
24 #define BAD_CLK_NAME ((const char *)-1)
33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
44 #define policy_exists(policy) ((policy)->offset != 0)
55 #define hyst_exists(hyst) ((hyst)->offset != 0)
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| /linux/drivers/clk/tegra/ |
| H A D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <linux/clk-provider.h>
61 * So below are the valid mask defines for each CLK_OUT_ENB register used to
73 * struct tegra_clk_sync_source - external clock source from codec
75 * @hw: handle between common and hardware-specific interfaces
95 * struct tegra_clk_frac_div - fractional divider clock
97 * @hw: handle between common and hardware-specific interfaces
98 * @reg: register containing divider
99 * @flags: hardware-specific flags
101 * @width: width of the divider bit field
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| /linux/drivers/clk/renesas/ |
| H A D | rzv2h-cpg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
15 * struct pll - Structure for PLL configuration
17 * @offset: STBY register offset
43 * struct ddiv - Structure for dynamic switching divider
45 * @offset: register offset
47 * @width: width of the divider
48 * @monbit: monitor bit in CPG_CLKSTATUS0 register
49 * @no_rmw: flag to indicate if the register is read-modify-write
55 unsigned int width:4; member
72 .width = _width, \
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| /linux/drivers/video/fbdev/ |
| H A D | vga16fb.c | 2 * linux/drivers/video/vga16.c -- VGA 16-color framebuffer driver
6 * Based on VESA framebuffer (c) 1998 Gerd Knorr <kraxel@goldbach.in-berlin.de>
34 /* --------------------------------------------------------------------- */
41 /* structure holding original VGA register settings when the
45 unsigned char CrtCtrlIndex; /* CRT-Contr. Index reg. */
46 unsigned char CrtMiscIO; /* Miscellaneous register */
47 unsigned char HorizontalTotal; /* CRT-Controller:00h */
48 unsigned char HorizDisplayEnd; /* CRT-Controller:01h */
49 unsigned char StartHorizRetrace;/* CRT-Controller:04h */
50 unsigned char EndHorizRetrace; /* CRT-Controller:05h */
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| /linux/drivers/clk/sprd/ |
| H A D | mux.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
14 * struct sprd_mux_ssel - Mux clock's source select bits in its register
15 * @shift: Bit offset of the divider in its register
16 * @width: Width of the divider field in its register
18 * chips, this matches the value of mux clock's register and the
23 u8 width; member
35 .width = _width, \
|
| /linux/drivers/media/platform/ti/omap3isp/ |
| H A D | isph3a_af.c | 1 // SPDX-License-Identifier: GPL-2.0-only
5 * TI OMAP3 ISP - H3A AF module
38 if (af->state == ISPSTAT_DISABLED) in h3a_af_setup_regs()
41 isp_reg_writel(af->isp, af->active_buf->dma_addr, OMAP3_ISP_IOMEM_H3A, in h3a_af_setup_regs()
44 if (!af->update) in h3a_af_setup_regs()
48 pax1 = ((conf->paxel.width >> 1) - 1) << AF_PAXW_SHIFT; in h3a_af_setup_regs()
50 pax1 |= (conf->paxel.height >> 1) - 1; in h3a_af_setup_regs()
51 isp_reg_writel(af->isp, pax1, OMAP3_ISP_IOMEM_H3A, ISPH3A_AFPAX1); in h3a_af_setup_regs()
53 /* Configure AFPAX2 Register */ in h3a_af_setup_regs()
54 /* Set Line Increment in AFPAX2 Register */ in h3a_af_setup_regs()
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| /linux/drivers/clk/samsung/ |
| H A D | clk.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <linux/clk-provider.h>
14 #include <linux/device-id/of.h>
16 #include "clk-pll.h"
17 #include "clk-cpu.h"
20 * struct samsung_clk_provider - information about clock provider
21 * @reg_base: virtual address for the register base
23 * @sysreg: syscon regmap for clock-provider sysreg controller
24 * @lock: maintains exclusion between callbacks for a given clock-provider
25 * @auto_clock_gate: enable auto clk mode for all clocks in clock-provider
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| /linux/arch/mips/boot/dts/mti/ |
| H A D | sead3.dts | 1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/mips-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 compatible = "mti,sead-3";
14 model = "MIPS SEAD-3";
17 stdout-path = "serial1:115200";
36 cpu_intc: interrupt-controller {
37 compatible = "mti,cpu-interrupt-controller";
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| /linux/drivers/clk/ |
| H A D | clk-axm5516.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/clk/clk-axm5516.c
16 #include <linux/clk-provider.h>
18 #include <dt-bindings/clock/lsi,axm5516-clks.h>
22 * struct axxia_clk - Common struct to all Axxia clocks.
33 * struct axxia_pllclk - Axxia PLL generated clock.
35 * @reg: Offset into regmap for PLL control register
44 * axxia_pllclk_recalc - Calculate the PLL generated clock rate given the
55 regmap_read(aclk->regmap, pll->reg, &control); in axxia_pllclk_recalc()
69 * struct axxia_divclk - Axxia clock divider
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| H A D | clk-divider.c | 1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
10 #include <linux/clk-provider.h>
24 * prepare - clk_prepare only ensures that parents are prepared
25 * enable - clk_enable only ensures that parents are enabled
26 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
27 * parent - fixed parent. No clk_set_parent support
32 if (divider->flags & CLK_DIVIDER_BIG_ENDIAN) in clk_div_readl()
33 return ioread32be(divider->reg); in clk_div_readl()
35 return readl(divider->reg); in clk_div_readl()
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| /linux/drivers/media/platform/renesas/ |
| H A D | renesas-ceu.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2017-2018 Jacopo Mondi <jacopo+renesas@jmondi.org>
6 * Based on soc-camera driver "soc_camera/sh_mobile_ceu_camera.c"
9 * Based on V4L2 Driver for PXA camera host - "pxa_camera.c",
16 #include <linux/dma-mapping.h>
32 #include <media/v4l2-async.h>
33 #include <media/v4l2-common.h>
34 #include <media/v4l2-ctrls.h>
35 #include <media/v4l2-dev.h>
36 #include <media/v4l2-device.h>
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