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Searched +full:reference +full:- +full:div2 +full:- +full:enable (Results 1 – 9 of 9) sorted by relevance

/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,adf4350.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michael Hennerich <michael.hennerich@analog.com>
15 - adi,adf4350
16 - adi,adf4351
21 spi-max-frequency:
26 description: Clock to provide CLKIN reference clock signal.
28 clock-names:
31 '#clock-cells':
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.c2 * Copyright © 2006-2016 Intel Corporation
47 * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
69 void (*enable)(struct intel_display *display,
129 shared_dpll[pll->index] = pll->state; in intel_atomic_duplicate_dpll_state()
138 drm_WARN_ON(s->dev, !drm_modeset_is_locked(&s->dev->mode_config.connection_mutex)); in intel_atomic_get_shared_dpll_state()
140 if (!state->dpll_se in intel_atomic_get_shared_dpll_state()
68 void (*enable)(struct drm_i915_private *i915, global() member
2924 int div2; icl_mg_pll_find_divisors() local
3205 u32 m1, m2_int, m2_frac, div1, div2, ref_clock; icl_ddi_mg_pll_get_freq() local
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/linux/drivers/thermal/tegra/
H A Dtegra30-tsensor.c1 // SPDX-License-Identifier: GPL-2.0
9 * Copyright (C) 2021 GRATE-DRIVER project
95 err = reset_control_assert(ts->rst); in tegra_tsensor_hw_enable()
97 dev_err(ts->dev, "failed to assert hardware reset: %d\n", err); in tegra_tsensor_hw_enable()
101 err = clk_prepare_enable(ts->clk); in tegra_tsensor_hw_enable()
103 dev_err(ts->dev, "failed to enable clock: %d\n", err); in tegra_tsensor_hw_enable()
109 err = reset_control_deassert(ts->rst); in tegra_tsensor_hw_enable()
111 dev_err(ts->dev, "failed to deassert hardware reset: %d\n", err); in tegra_tsensor_hw_enable()
119 * M: number of reference clock pulses after which every in tegra_tsensor_hw_enable()
122 * N: number of reference clock counts for which the counter runs in tegra_tsensor_hw_enable()
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/linux/drivers/video/fbdev/
H A Dcyber2000fb.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 1998-2002 Russell King
49 #include <linux/i2c-algo-bit.h>
52 #include <asm/mach-types.h>
109 #define cyber2000fb_writel(val, reg, cfb) writel(val, (cfb)->regs + (reg))
110 #define cyber2000fb_writew(val, reg, cfb) writew(val, (cfb)->regs + (reg))
111 #define cyber2000fb_writeb(val, reg, cfb) writeb(val, (cfb)->regs + (reg))
113 #define cyber2000fb_readb(reg, cfb) readb((cfb)->regs + (reg))
149 /* -------------------- Hardware specific routines ------------------------- */
160 if (!(cfb->fb.var.accel_flags & FB_ACCELF_TEXT)) { in cyber2000fb_fillrect()
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H A Damifb.c2 * linux/drivers/video/amifb.c -- Amiga builtin chipset frame buffer device
4 * Copyright (C) 1995-2003 Geert Uytterhoeven
30 * - 24 Jul 96: Copper generates now vblank interrupt and
32 * - 14 Jul 96: Rework and hopefully last ECS bugs fixed
33 * - 7 Mar 96: Hardware sprite support by Roman Zippel
34 * - 18 Feb 96: OCS and ECS support by Roman Zippel
36 * - 2 Dec 95: AGA version by Geert Uytterhoeven
107 ---------------------
111 +----------+---------------------------------------------+----------+-------+
115 +----------###############################################----------+-------+
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/linux/drivers/media/dvb-frontends/
H A Dstb0899_algo.c1 // SPDX-License-Identifier: GPL-2.0-or-later
50 struct stb0899_internal *internal = &state->internal;
55 return stb0899_calc_srate(internal->master_clk, sfr);
71 dprintk(state->verbose, FE_DEBUG, 1, "-->"); in stb0899_set_srate()
122 struct stb0899_internal *internal = &state->internal; in stb0899_carr_width()
124 return (internal->srate + (internal->srate * internal->rolloff) / 100); in stb0899_carr_width()
133 struct stb0899_internal *internal = &state->internal; in stb0899_first_subrange()
134 struct stb0899_params *params = &state->params; in stb0899_first_subrange()
135 struct stb0899_config *config = state->config; in stb0899_first_subrange()
140 if (config->tuner_get_bandwidth) { in stb0899_first_subrange()
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/linux/include/dt-bindings/clock/
H A Dtegra234-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
294 /** @brief controls MPHY_FORCE_LS_MODE upon enable & disable */
458 /** @brief PLLC4 VCO followed by DIV2 path */
842 /** @brief VPLL0 reference clock */
848 /** @brief NVDISPLAY_P0_CLK reference select */
890 /** @brief output of fixed (DIV2) MC HUB divider */
/linux/drivers/comedi/drivers/
H A Dni_labpc_common.c1 // SPDX-License-Identifier: GPL-2.0+
7 * Copyright (C) 2001-2003 Frank Mori Hess <fmhess@users.sourceforge.net>
86 return inb(dev->iobase + reg); in labpc_inb()
92 outb(byte, dev->iobase + reg); in labpc_outb()
99 return readb(dev->mmio + reg); in labpc_readb()
105 writeb(byte, dev->mmio + reg); in labpc_writeb()
110 struct labpc_private *devpriv = dev->private; in labpc_cancel()
113 spin_lock_irqsave(&dev->spinlock, flags); in labpc_cancel()
114 devpriv->cmd2 &= ~(CMD2_SWTRIG | CMD2_HWTRIG | CMD2_PRETRIG); in labpc_cancel()
115 devpriv->write_byte(dev, devpriv->cmd2, CMD2_REG); in labpc_cancel()
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/linux/drivers/clk/stm32/
H A Dclk-stm32mp1.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
9 #include <linux/clk-provider.h>
17 #include <linux/reset-controller.h>
21 #include <dt-bindings/clock/stm32mp1-clks.h>
23 #include "reset-stm32.h"
171 "ck_hse", "pll4_r", "clk-hse-div2"
397 struct gate_cfg *gate_cfg = cfg->cfg; in _clk_hw_register_gate()
400 cfg->name, in _clk_hw_register_gate()
401 cfg->parent_name, in _clk_hw_register_gate()
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