Home
last modified time | relevance | path

Searched full:rcr2 (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/rtc/
H A Drtc-sh.c59 #define RCR2 RTC_REG(15) /* Control */ macro
82 /* RCR2 Bits */
143 if (!(readb(rtc->regbase + RCR2) & RCR2_RTCEN)) in sh_rtc_read_time()
203 tmp = readb(rtc->regbase + RCR2); in sh_rtc_set_time()
206 writeb(tmp, rtc->regbase + RCR2); in sh_rtc_set_time()
225 tmp = readb(rtc->regbase + RCR2); in sh_rtc_set_time()
228 writeb(tmp, rtc->regbase + RCR2); in sh_rtc_set_time()
H A Drtc-renesas-rtca3.c215 * registers, year alarm enable register, bits RCR2.AADJE, AADJP, in rtca3_prepare_cntalrm_regs_for_read()
287 u8 rcr2, tmp; in rtca3_set_time() local
293 rcr2 = readb(priv->base + RTCA3_RCR2); in rtca3_set_time()
294 writeb(rcr2 & ~RTCA3_RCR2_START, priv->base + RTCA3_RCR2); in rtca3_set_time()
314 writeb(rcr2 | RTCA3_RCR2_START, priv->base + RTCA3_RCR2); in rtca3_set_time()
537 /* RADJ.PMADJ need to be set to zero before setting RCR2.ADJP. */ in rtca3_set_offset()
650 * (RCR2.START bit = 1) to be able to read the counters after a return from in rtca3_initial_setup()
862 * RCR2.START = 1 to be able to read the counters after a return from low in rtca3_resume()
/linux/sound/soc/ti/
H A Domap-mcbsp.c47 dev_dbg(mcbsp->dev, "RCR2: 0x%04x\n", MCBSP_READ(mcbsp, RCR2)); in omap_mcbsp_dump_reg()
184 MCBSP_WRITE(mcbsp, RCR2, config->rcr2); in omap_mcbsp_config()
988 regs->rcr2 &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7)); in omap_mcbsp_dai_hw_params()
997 regs->rcr2 |= RPHASE; in omap_mcbsp_dai_hw_params()
1001 regs->rcr2 |= RFRLEN2(wpf - 1); in omap_mcbsp_dai_hw_params()
1011 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_16); in omap_mcbsp_dai_hw_params()
1018 regs->rcr2 |= RWDLEN2(OMAP_MCBSP_WORD_32); in omap_mcbsp_dai_hw_params()
1087 regs->rcr2 |= RFIG; in omap_mcbsp_dai_set_dai_fmt()
1100 regs->rcr2 |= RDATDLY(1); in omap_mcbsp_dai_set_dai_fmt()
1105 regs->rcr2 |= RDATDLY(0); in omap_mcbsp_dai_set_dai_fmt()
[all …]
H A Domap-mcbsp-priv.h122 /*************************** McBSP RCR2 bit definitions ***********************/
214 u16 rcr2; member
/linux/sound/soc/fsl/
H A Dfsl_sai.c562 * 1) For Asynchronous mode, we must set RCR2 register for capture, and in fsl_sai_hw_params()
564 * 2) For Tx sync with Rx clock, we must set RCR2 register for playback in fsl_sai_hw_params()