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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dqoriq-clock.txt1 * Clock Block on Freescale QorIQ Platforms
3 Freescale QorIQ chips take primary clocking input from the external
5 multiple phase locked loops (PLL) to create a variety of frequencies
10 All references to "1.0" and "2.0" refer to the QorIQ chassis version to
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
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H A Dfsl,qoriq-clock-legacy.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock-legacy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Legacy Clock Block on Freescale QorIQ Platforms
10 - Frank Li <Frank.Li@nxp.com>
16 Most of the bindings are from the common clock binding[1].
17 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
22 - fsl,qoriq-core-pll-1.0
23 - fsl,qoriq-core-pll-2.0
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H A Dfsl,qoriq-clock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/fsl,qoriq-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Clock Block on Freescale QorIQ Platforms
10 - Frank Li <Frank.Li@nxp.com>
13 Freescale QorIQ chips take primary clocking input from the external
15 multiple phase locked loops (PLL) to create a variety of frequencies
20 All references to "1.0" and "2.0" refer to the QorIQ chassis version to
24 --------------- -------------
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H A Dfsl,plldig.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP QorIQ Layerscape LS1028A Display PIXEL Clock
10 - Wen He <wen.he_1@nxp.com>
14 interface in the display core, as implemented in TSMC CLN28HPM PLL.
19 const: fsl,ls1028a-plldig
22 maxItems: 1
25 maxItems: 1
27 '#clock-cells':
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