/linux/Documentation/netlink/specs/ |
H A D | devlink.yaml | 1239 post: devlink-nl-post-doit 1262 post: devlink-nl-post-doit 1287 post: devlink-nl-post-doit 1304 post: devlink-nl-post-doit 1326 post: devlink-nl-post-doit 1338 post: devlink-nl-post-doit 1354 post: devlink-nl-post-doit 1365 post: devlink-nl-post-doit 1387 post: devlink-nl-post-doit 1411 post: devlink-nl-post-doit [all …]
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H A D | dpll.yaml | 411 post: dpll-unlock-doit 430 post: dpll-post-doit 457 post: dpll-post-doit 485 post: dpll-unlock-doit 513 post: dpll-pin-post-doit 551 post: dpll-pin-post-doit
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/linux/Documentation/livepatch/ |
H A D | callbacks.rst | 42 * Post-patch 48 active), used to clean up post-patch callback 51 * Post-unpatch 61 symmetry: pre-patch callbacks have a post-unpatch counterpart and 62 post-patch callbacks have a pre-unpatch counterpart. An unpatch 90 No post-patch, pre-unpatch, or post-unpatch callbacks will be executed 96 will only occur if their corresponding post-patch callback executed). 100 only the post-unpatch callback will be called. 118 patch the data *after* patching is complete with a post-patch callback, 126 may be possible to implement similar updates via pre/post-patch [all …]
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/linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ |
H A D | gm200.c | 83 pmu_load(struct nv50_devinit *init, u8 type, bool post, in pmu_load() argument 94 if (!post || !subdev->device->pmu) in pmu_load() 115 gm200_devinit_preos(struct nv50_devinit *init, bool post) in gm200_devinit_preos() argument 120 pmu_load(init, 0x01, post, NULL, NULL); in gm200_devinit_preos() 124 gm200_devinit_post(struct nvkm_devinit *base, bool post) in gm200_devinit_post() argument 141 ret = pmu_load(init, 0x04, post, &exec, &args); in gm200_devinit_post() 148 if (post) { in gm200_devinit_post() 156 if (post) { in gm200_devinit_post() 164 if (post) { in gm200_devinit_post() 174 gm200_devinit_preos(init, post); in gm200_devinit_post() [all …]
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H A D | base.c | 63 if (init && init->func->post) in nvkm_devinit_post() 64 ret = init->func->post(init, init->post); in nvkm_devinit_post() 75 init->post = true; in nvkm_devinit_fini() 87 /* Override the post flag during the first call if NvForcePost is set */ in nvkm_devinit_preinit() 89 init->post = init->force_post; in nvkm_devinit_preinit()
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H A D | nv50.c | 98 * missing, assume it's a secondary gpu which requires post in nv50_devinit_preinit() 100 if (!base->post) { in nv50_devinit_preinit() 103 base->post = true; in nv50_devinit_preinit() 109 if (!base->post) { in nv50_devinit_preinit() 113 base->post = true; in nv50_devinit_preinit() 134 while (init->base.post && dcb_outp_parse(bios, i, &ver, &hdr, &outp)) { in nv50_devinit_init() 165 .post = nv04_devinit_post,
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/linux/tools/testing/selftests/livepatch/ |
H A D | test-callbacks.sh | 22 # according to the klp_patch, their post-patch callbacks run and the 26 # unpatching transition starts. klp_objects are reverted, post-patch 67 # - On livepatch enable, only pre/post-patch callbacks are executed for 71 # pre/post-patch callbacks are executed. 74 # $MOD_TARGET) pre/post-unpatch callbacks are executed. 119 # post-unpatch callbacks are executed when this occurs. 121 # - When the livepatch is disabled, pre and post-unpatch callbacks are 166 # pre/post-patch callbacks are executed. 170 # post-unpatch callbacks are executed when this occurs. 213 # - As expected, only pre/post-(un)patch handlers are executed for [all …]
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/linux/drivers/media/i2c/cx25840/ |
H A D | cx25840-audio.c | 39 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq() 40 * AUX_PLL Integer = 0x06, AUX PLL Post Divider = 0x10 in cx25840_set_audclk_freq() 61 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq() 77 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq() 78 * AUX_PLL Integer = 0x09, AUX PLL Post Divider = 0x10 in cx25840_set_audclk_freq() 98 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq() 114 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq() 115 * AUX_PLL Integer = 0x0a, AUX PLL Post Divider = 0x10 in cx25840_set_audclk_freq() 135 * SA_MCLK_DIV = 0x10 = 384/384 * AUX_PLL post dvivider in cx25840_set_audclk_freq() 153 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in cx25840_set_audclk_freq() [all …]
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/linux/drivers/md/dm-vdo/indexer/ |
H A D | index-session.h | 28 /* Post requests that found an entry */ in __aligned() 30 /* Post requests found in the open chapter */ in __aligned() 32 /* Post requests found in the dense index */ in __aligned() 34 /* Post requests found in the sparse index */ in __aligned() 36 /* Post requests that did not find an entry */ in __aligned()
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/linux/drivers/gpu/drm/ci/ |
H A D | gitlab-ci.yml | 144 # Post-merge pipeline 145 - if: &is-post-merge '$CI_PROJECT_NAMESPACE == "mesa" && $CI_COMMIT_BRANCH' 147 # Post-merge pipeline, not for Marge Bot 148 …- if: &is-post-merge-not-for-marge '$CI_PROJECT_NAMESPACE == "mesa" && $GITLAB_USER_LOGIN != "marg… 157 .never-post-merge-rules: 159 - if: *is-post-merge 179 - !reference [.never-post-merge-rules, rules] 187 - !reference [.never-post-merge-rules, rules] 206 - !reference [.never-post-merge-rules, rules] 209 - if: *is-post-merge [all …]
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/linux/Documentation/devicetree/bindings/clock/ |
H A D | keystone-pll.txt | 2 a divider and a post divider. The additional PLL IPs like ARMPLL, DDRPLL 16 - reg-names : control, multiplier and post-divider. The multiplier and 17 post-divider registers are applicable only for main pll clock 18 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits 27 reg-names = "control", "multiplier", "post-divider";
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/linux/Documentation/ABI/testing/ |
H A D | sysfs-bus-iio-adc-ad4130 | 24 * "sinc3+pf1" - Sinc3 + Post Filter 1. 53dB rejection @ 27 * "sinc3+pf2" - Sinc3 + Post Filter 2. 70dB rejection @ 30 * "sinc3+pf3" - Sinc3 + Post Filter 3. 99dB rejection @ 33 * "sinc3+pf4" - Sinc3 + Post Filter 4. 103dB rejection @
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H A D | configfs-most | 60 configuration, the creation is post-poned until 115 configuration, the creation is post-poned until 170 configuration, the creation is post-poned until 236 configuration, the creation is post-poned until
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/linux/drivers/media/pci/cx18/ |
H A D | cx18-av-audio.c | 60 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq() 61 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x20 in set_audclk_freq() 95 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq() 96 * AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x18 in set_audclk_freq() 130 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq() 131 * AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x16 in set_audclk_freq() 167 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq() 168 * AUX_PLL Integer = 0x0d, AUX PLL Post Divider = 0x30 in set_audclk_freq() 206 * VID_PLL Integer = 0x0f, VID_PLL Post Divider = 0x04 in set_audclk_freq() 207 * AUX_PLL Integer = 0x0e, AUX PLL Post Divider = 0x24 in set_audclk_freq() [all …]
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/linux/drivers/video/fbdev/matrox/ |
H A D | matroxfb_misc.h | 9 unsigned int* in, unsigned int* feed, unsigned int* post); 13 unsigned int *post) in PLL_calcclock() argument 15 return matroxfb_PLL_calcclock(&minfo->features.pll, freq, fmax, in, feed, post); in PLL_calcclock()
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/linux/drivers/net/ethernet/mellanox/mlx5/core/en/tc/ |
H A D | post_act.c | 53 mlx5_core_warn(priv->mdev, "failed to create post action table, err: %d\n", err); in mlx5e_tc_post_act_init() 93 /* Post action rule matches on fte_id and executes original rule's tc rule action */ in mlx5e_tc_post_act_offload() 99 netdev_warn(post_act->priv->netdev, "Failed to add post action rule"); in mlx5e_tc_post_act_offload() 133 /* Splits were handled before post action */ in mlx5e_tc_post_act_add() 174 /* Allocate a header modify action to write the post action handle fte id to a register. */
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/linux/drivers/clk/sophgo/ |
H A D | clk-cv18xx-pll.c | 54 unsigned long pre, div, post; in ipll_find_rate() local 60 for_each_pll_limit_range(post, &limit->post_div) { in ipll_find_rate() 61 tmp = ipll_calc_rate(prate, pre, div, post); in ipll_find_rate() 70 post_div_sel = post; in ipll_find_rate() 290 unsigned long pre, div, post; in fpll_find_rate() local 298 for_each_pll_limit_range(post, &limit->post_div) { in fpll_find_rate() 301 pre, div, post, in fpll_find_rate() 309 post_div_sel = post; in fpll_find_rate()
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/linux/drivers/clk/qcom/ |
H A D | clk-alpha-pll.h | 101 * struct clk_alpha_pll_postdiv - phase locked loop (PLL) post-divider 104 * @width: width of post-divider 105 * @post_div_shift: shift to differentiate between odd & even post-divider 106 * @post_div_table: table with PLL odd and even post-divider settings 107 * @num_post_div: Number of PLL post-divider settings
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/linux/tools/testing/selftests/tc-testing/creating-plugins/ |
H A D | AddingPlugins.txt | 23 post (the post-suite stage) 52 post-suite method using this info passed in to the pre_suite method. 82 'post'
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/linux/drivers/gpu/drm/i915/gt/ |
H A D | gen6_engine_cs.c | 18 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for 24 * send a PIPE_CONTROL with no bits set except Post-Sync Operation != 28 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. 33 * BEFORE the pipe-control with a post-sync op and no write-cache 45 * - Post-Sync Operation ([13] of DW1) 50 * Post-sync nonzero is what triggered this second workaround, so we 125 * TLB invalidate requires a post-sync write. in gen6_emit_flush_rcs() 200 * Post-Sync Operation field is a value of 1h or 3h." in mi_flush_dw() 307 * CS_STALL suggests at least a post-sync write. in gen7_emit_flush_rcs()
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/linux/tools/testing/selftests/drivers/net/netdevsim/ |
H A D | devlink.sh | 125 check_value max_macs post-set 16 32 126 check_value test1 post-set false Y 130 check_value max_macs post-reload 16 16 131 check_value test1 post-reload false N 170 check_region_snapshot_count dummy post-first-snapshot 1 174 check_region_snapshot_count dummy post-second-snapshot 2 178 check_region_snapshot_count dummy post-third-snapshot 3 183 check_region_snapshot_count dummy post-first-delete 2 188 check_region_snapshot_count dummy post-first-request 3 208 check_region_snapshot_count dummy post-second-delete 2 [all …]
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/linux/sound/core/ |
H A D | pcm_timer.c | 21 unsigned long rate, mult, fsize, l, post; in snd_pcm_timer_resolution_change() local 37 post = 1; in snd_pcm_timer_resolution_change() 40 post *= 2; in snd_pcm_timer_resolution_change() 49 runtime->timer_resolution = (mult * fsize / rate) * post; in snd_pcm_timer_resolution_change()
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/linux/drivers/infiniband/hw/qedr/ |
H A D | qedr_roce_cm.c | 430 DP_ERR(dev, "gsi post send: failed to init header\n"); in qedr_gsi_build_header() 553 "gsi post recv: failed to post rx buffer. state is %d and not QED_ROCE_QP_STATE_RTS\n", in qedr_gsi_post_send() 559 DP_ERR(dev, "gsi post send: num_sge is too large (%d>%d)\n", in qedr_gsi_post_send() 567 "gsi post send: failed due to unsupported opcode %d\n", in qedr_gsi_post_send() 587 "gsi post send: opcode=%d, wr_id=%llx\n", wr->opcode, in qedr_gsi_post_send() 590 DP_ERR(dev, "gsi post send: failed to transmit (rc=%d)\n", rc); in qedr_gsi_post_send() 599 "gsi post send: failed second WR. Only one WR may be passed at a time\n"); in qedr_gsi_post_send() 623 "gsi post recv: failed to post rx buffer. state is %d and not QED_ROCE_QP_STATE_RTR/S\n", in qedr_gsi_post_recv() 633 "gsi post recv: failed to post rx buffer. too many sges %d>%d\n", in qedr_gsi_post_recv() 646 "gsi post recv: failed to post rx buffer (rc=%d)\n", in qedr_gsi_post_recv()
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/linux/drivers/mmc/core/ |
H A D | core.h | 171 * mmc_post_req - Post process a completed request 172 * @host: MMC host to post process command 173 * @mrq: MMC request to post process for 176 * Let the host post process a completed request. Post processing of
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/linux/drivers/clk/analogbits/ |
H A D | wrpll-cln28hpc.c | 41 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */ 44 /* MAX_POST_DIVIDE_REF_FREQ: maximum post-divider reference frequency, in Hz */ 77 * on the input clock frequency after the post-R-divider @post_divr_freq. 88 WARN(1, "%s: post-divider reference freq out of range: %lu", in __wrpll_calc_filter_range() 138 * Determine a reasonable value for the PLL Q post-divider, based on the 208 * @target_rate: target PLL output clock rate (post-Q-divider) 326 * post-divider).
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