| /linux/Documentation/devicetree/bindings/soundwire/ |
| H A D | qcom,soundwire.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
11 - Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
19 - enum:
20 - qcom,soundwire-v1.3.0
21 - qcom,soundwire-v1.5.0
22 - qcom,soundwire-v1.5.1
23 - qcom,soundwire-v1.6.0
[all …]
|
| /linux/drivers/net/ethernet/netronome/nfp/nfpcore/ |
| H A D | nfp_nsp_eth.c | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 /* Copyright (C) 2015-2017 Netronome Systems, Inc. */
84 __le64 control; member
128 dst[ETH_ALEN - i - 1] = src[i]; in nfp_eth_copy_mac_reverse()
139 port = le64_to_cpu(src->port); in nfp_eth_port_translate()
140 state = le64_to_cpu(src->state); in nfp_eth_port_translate()
142 dst->eth_index = FIELD_GET(NSP_ETH_PORT_INDEX, port); in nfp_eth_port_translate()
143 dst->index = index; in nfp_eth_port_translate()
144 dst->nbi = index / NSP_ETH_NBI_PORT_COUNT; in nfp_eth_port_translate()
145 dst->base = index % NSP_ETH_NBI_PORT_COUNT; in nfp_eth_port_translate()
[all …]
|
| /linux/Documentation/devicetree/bindings/phy/ |
| H A D | nvidia,tegra124-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
17 documentation. Each such "pad" may control either one or multiple lanes,
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
[all …]
|
| H A D | nvidia,tegra186-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
17 documentation. Each such "pad" may control either one or multiple lanes,
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
[all …]
|
| H A D | nvidia,tegra194-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra194-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
17 documentation. Each such "pad" may control either one or multiple lanes,
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
[all …]
|
| H A D | nvidia,tegra210-xusb-padctl.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 signals) which connect directly to pins/pads on the SoC package. Each lane
17 documentation. Each such "pad" may control either one or multiple lanes,
18 and thus contains any logic common to all its lanes. Each lane can be
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
[all …]
|
| /linux/Documentation/devicetree/bindings/media/i2c/ |
| H A D | maxim,max96714.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Maxim MAX96714 GMSL2 to CSI-2 Deserializer
11 - Julien Massot <julien.massot@collabora.com>
15 CSI-2 D-PHY formatted output. The device allows the GMSL2 link to
16 simultaneously transmit bidirectional control-channel data while forward
18 remotely located serializer using industry-standard coax or STP
30 - const: maxim,max96714f
31 - items:
[all …]
|
| H A D | maxim,max96717.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 ---
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: MAX96717 CSI-2 to GMSL2 Serializer
11 - Julien Massot <julien.massot@collabora.com>
14 The MAX96717 serializer converts MIPI CSI-2 D-PHY formatted input
16 simultaneously transmit bidirectional control-channel data while forward
18 remotely located deserializer using industry-standard coax or STP
32 - const: maxim,max96717f
33 - items:
[all …]
|
| /linux/drivers/thunderbolt/ |
| H A D | switch.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Thunderbolt driver - switch/port utility functions
12 #include <linux/nvmem-provider.h>
42 if (uuid_equal(&st->uuid, sw->uuid)) in __nvm_get_auth_status()
57 *status = st ? st->status : 0; in nvm_get_auth_status()
64 if (WARN_ON(!sw->uuid)) in nvm_set_auth_status()
75 memcpy(&st->uuid, sw->uuid, sizeof(st->uuid)); in nvm_set_auth_status()
76 INIT_LIST_HEAD(&st->list); in nvm_set_auth_status()
77 list_add_tail(&st->list, &nvm_auth_status_cache); in nvm_set_auth_status()
80 st->status = status; in nvm_set_auth_status()
[all …]
|
| H A D | acpi.c | 1 // SPDX-License-Identifier: GPL-2.0
26 fwnode = fwnode_find_reference(acpi_fwnode_handle(adev), "usb4-host-interface", 0); in tb_acpi_add_link()
31 if (dev_fwnode(&nhi->pdev->dev) != fwnode) in tb_acpi_add_link()
35 * Ignore USB3 ports here as USB core will set up device links between in tb_acpi_add_link()
37 * USB3 ports might not even have a physical device yet if xHCI driver in tb_acpi_add_link()
58 pm_runtime_get_sync(&pdev->dev); in tb_acpi_add_link()
60 link = device_link_add(&pdev->dev, &nhi->pdev->dev, in tb_acpi_add_link()
65 dev_dbg(&nhi->pdev->dev, "created link from %s\n", in tb_acpi_add_link()
66 dev_name(&pdev->dev)); in tb_acpi_add_link()
69 dev_warn(&nhi->pdev->dev, "device link creation from %s failed\n", in tb_acpi_add_link()
[all …]
|
| H A D | tb.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Thunderbolt driver - bus logic (NHI independent)
13 #include <linux/nvmem-provider.h>
31 * struct tb_nvm - Structure holding NVM information
38 * @non_active: Non-active portion NVMem device
79 * enum tb_switch_tmu_mode - TMU mode
81 * @TB_SWITCH_TMU_MODE_LOWRES: Uni-directional, normal mode
82 * @TB_SWITCH_TMU_MODE_HIFI_UNI: Uni-directional, HiFi mode
83 * @TB_SWITCH_TMU_MODE_HIFI_BI: Bi-directional, HiFi mode
84 * @TB_SWITCH_TMU_MODE_MEDRES_ENHANCED_UNI: Enhanced Uni-directional, MedRes mode
[all …]
|
| /linux/drivers/phy/tegra/ |
| H A D | xusb-tegra186.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
282 writel(value, priv->ao_regs + offset); in ao_writel()
287 return readl(priv->ao_regs + offset); in ao_readl()
306 return ERR_PTR(-ENOMEM); in tegra186_usb2_lane_probe()
308 INIT_LIST_HEAD(&usb2->base.list); in tegra186_usb2_lane_probe()
309 usb2->base.soc = &pad->soc->lanes[index]; in tegra186_usb2_lane_probe()
310 usb2->base.index = index; in tegra186_usb2_lane_probe()
311 usb2->base.pad = pad; in tegra186_usb2_lane_probe()
[all …]
|
| H A D | xusb-tegra210.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
27 ((x) ? (11 + ((x) - 1) * 6) : 0)
447 static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane) in tegra210_usb3_lane_map() argument
451 for (map = tegra210_usb3_map; map->type; map++) { in tegra210_usb3_lane_map()
452 if (map->index == lane->index && in tegra210_usb3_lane_map()
453 strcmp(map->type, lane->pad->soc->name) == 0) { in tegra210_usb3_lane_map()
454 dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n", in tegra210_usb3_lane_map()
455 lane->pad->soc->lanes[lane->index].name, map->port); in tegra210_usb3_lane_map()
456 return map->port; in tegra210_usb3_lane_map()
[all …]
|
| /linux/drivers/soundwire/ |
| H A D | generic_bandwidth_allocation.c | 1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 // Copyright(c) 2015-2020 Intel Corporation.
21 unsigned int lane; member
42 struct sdw_bus_params *b_params = &m_rt->bus->params; in sdw_compute_slave_ports()
44 port_bo = t_data->block_offset; in sdw_compute_slave_ports()
46 list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) { in sdw_compute_slave_ports()
47 rate = m_rt->stream->params.rate; in sdw_compute_slave_ports()
48 bps = m_rt->stream->params.bps; in sdw_compute_slave_ports()
49 sample_int = (m_rt->bus->params.curr_dr_freq / rate); in sdw_compute_slave_ports()
52 list_for_each_entry(p_rt, &s_rt->port_list, port_node) { in sdw_compute_slave_ports()
[all …]
|
| /linux/drivers/phy/marvell/ |
| H A D | phy-mvebu-a3700-comphy.c | 1 // SPDX-License-Identifier: GPL-2.0
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
40 * When accessing common PHY lane registers directly, we need to shift by 1,
41 * since the registers are 16-bit.
175 * This register is not from PHY lane register space. It only exists in the
176 * indirect register space, before the actual PHY lane 2 registers. So the
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f)) argument
227 unsigned int lane; member
234 .lane = _lane, \
246 /* lane 0 */
[all …]
|
| /linux/include/linux/soundwire/ |
| H A D | sdw.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
68 * constants for flow control, ports and transport
87 * enum sdw_slave_status - Slave status
105 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare
106 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare
116 * enum sdw_command_response - Command response as defined by SDW spec
204 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a
215 * enum sdw_dpn_type - Data port types
230 * enum sdw_clk_stop_mode - Clock Stop modes
[all …]
|
| /linux/drivers/usb/host/ |
| H A D | xhci-hub.c | 1 // SPDX-License-Identifier: GPL-2.0
18 #include "xhci-trace.h"
24 /* Default sublink speed attribute of each lane */
54 bos->bLength = USB_DT_BOS_SIZE; in xhci_create_usb3x_bos_desc()
55 bos->bDescriptorType = USB_DT_BOS; in xhci_create_usb3x_bos_desc()
56 bos->wTotalLength = cpu_to_le16(USB_DT_BOS_SIZE + in xhci_create_usb3x_bos_desc()
58 bos->bNumDeviceCaps = 1; in xhci_create_usb3x_bos_desc()
61 for (i = 0; i < xhci->num_port_caps; i++) { in xhci_create_usb3x_bos_desc()
62 u8 major = xhci->port_caps[i].maj_rev; in xhci_create_usb3x_bos_desc()
63 u8 minor = xhci->port_caps[i].min_rev; in xhci_create_usb3x_bos_desc()
[all …]
|
| /linux/Documentation/ABI/testing/ |
| H A D | sysfs-bus-usb | 10 This allows to avoid side-effects with drivers
28 drivers, non-authorized one are not. By default, wired
33 Contact: linux-usb@vger.kernel.org
67 What: /sys/bus/usb-serial/drivers/.../new_id
69 Contact: linux-usb@vger.kernel.org
72 extra bus folder "usb-serial" in sysfs; apart from that
97 If CONFIG_PM is set and a USB 2.0 lpm-capable device is plugged
113 If CONFIG_PM is set and a USB 3.0 lpm-capable device is plugged
141 attribute allows user-space to know whether the device is
145 an on-screen keyboard if the only wireless keyboard is
[all …]
|
| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | mediatek,mt7621-pcie.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek,mt7621-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergio Paracuellos <sergio.paracuellos@gmail.com>
14 with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link
18 .-------.
22 '-------'
27 .------------------.
28 .-----------| HOST/PCI Bridge |------------.
[all …]
|
| H A D | nvidia,tegra20-pcie.txt | 4 - compatible: Must be:
5 - "nvidia,tegra20-pcie": for Tegra20
6 - "nvidia,tegra30-pcie": for Tegra30
7 - "nvidia,tegra124-pcie": for Tegra124 and Tegra132
8 - "nvidia,tegra210-pcie": for Tegra210
9 - "nvidia,tegra186-pcie": for Tegra186
10 - power-domains: To ungate power partition by BPMP powergate driver. Must
13 - device_type: Must be "pci"
14 - reg: A list of physical base address and length for each set of controller
15 registers. Must contain an entry for each entry in the reg-names property.
[all …]
|
| /linux/arch/arm/boot/dts/marvell/ |
| H A D | armada-xp-synology-ds414.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 * The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
12 * were delivered with an older version of u-boot that left internal
17 * installing it from u-boot prompt) or adjust the Devive Tree
21 /dts-v1/;
23 #include <dt-bindings/input/input.h>
24 #include <dt-bindings/gpio/gpio.h>
25 #include "armada-xp-mv78230.dtsi"
29 compatible = "synology,ds414", "marvell,armadaxp-mv78230",
30 "marvell,armadaxp", "marvell,armada-370-xp";
[all …]
|
| /linux/arch/mips/pci/ |
| H A D | pcie-octeon.c | 17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-pciercx-defs.h>
19 #include <asm/octeon/cvmx-pescx-defs.h>
20 #include <asm/octeon/cvmx-pexp-defs.h>
21 #include <asm/octeon/cvmx-pemx-defs.h>
22 #include <asm/octeon/cvmx-dpi-defs.h>
23 #include <asm/octeon/cvmx-sli-defs.h>
24 #include <asm/octeon/cvmx-sriox-defs.h>
25 #include <asm/octeon/cvmx-helper-errata.h>
26 #include <asm/octeon/pci-octeon.h>
[all …]
|
| /linux/include/linux/ |
| H A D | thunderbolt.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
46 * enum tb_security_level - Thunderbolt security level
67 * struct tb - main thunderbolt bus structure
72 * @ctl: Control channel for this domain
103 return (link - 1) / TB_LINKS_PER_PHY_PORT; in tb_phy_port_from_link()
107 * struct tb_property_dir - XDomain property directory
129 * struct tb_property - XDomain property
181 * enum tb_link_width - Thunderbolt/USB4 link width
182 * @TB_LINK_WIDTH_SINGLE: Single lane link
183 * @TB_LINK_WIDTH_DUAL: Dual lane symmetric link
[all …]
|
| /linux/Documentation/networking/ |
| H A D | phy.rst | 26 #. Increase code-reuse
27 #. Increase overall code-maintainability
67 for one of the users. (e.g. "git grep fsl,.*-mdio arch/powerpc/boot/dts/")
72 The Reduced Gigabit Medium Independent Interface (RGMII) is a 12-pin
84 or the PCB traces insert the correct 1.5-2ns delay
97 * PHY devices may offer sub-nanosecond granularity in how they allow a
115 PHY_INTERFACE_MODE_RGMII, it should make sure that the MAC-level delays are
130 -----------------------------------------
197 PHY-specific flags should be set in phydev->dev_flags prior to the call
208 Now just make sure that phydev->supported and phydev->advertising have any
[all …]
|
| /linux/drivers/net/dsa/mv88e6xxx/ |
| H A D | chip.h | 1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Marvell 88E6xxx Ethernet switch single-chip definition
30 /* PVT limits for 4-bit port and 5-bit switch */
112 * enum mv88e6xxx_edsa_support - Ethertype DSA tag support level
150 /* Mark certain ports as invalid. This is required for example for the
151 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
152 * ports 2-4 are not routet to pins.
155 /* Multi-chip Addressing Mode.
157 * when it is non-zero, and use indirect access to internal registers.
160 /* Dual-chip Addressing Mode
[all …]
|