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Searched full:pllclk (Results 1 – 7 of 7) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dsophgo,sg2042-clkgen.yaml52 clocks = <&pllclk 0>,
53 <&pllclk 1>,
54 <&pllclk 2>,
55 <&pllclk 3>;
H A Dstarfive,jh7110-syscrg.yaml109 <&pllclk 0>, <&pllclk 1>, <&pllclk 2>;
/linux/drivers/clk/starfive/
H A Dclk-starfive-jh7110-sys.c408 struct clk *pllclk; in jh7110_syscrg_probe() local
424 pllclk = clk_get(priv->dev, "pll0_out"); in jh7110_syscrg_probe()
425 if (IS_ERR(pllclk)) { in jh7110_syscrg_probe()
433 ret = clk_notifier_register(pllclk, &priv->pll_clk_nb); in jh7110_syscrg_probe()
439 pllclk = clk_get(priv->dev, "pll1_out"); in jh7110_syscrg_probe()
440 if (IS_ERR(pllclk)) { in jh7110_syscrg_probe()
447 clk_put(pllclk); in jh7110_syscrg_probe()
451 pllclk = clk_get(priv->dev, "pll2_out"); in jh7110_syscrg_probe()
452 if (IS_ERR(pllclk)) { in jh7110_syscrg_probe()
459 clk_put(pllclk); in jh7110_syscrg_probe()
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-common.dtsi345 <&pllclk JH7110_PLLCLK_PLL0_OUT>;
346 assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
347 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
348 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
H A Djh7110.dtsi898 <&pllclk JH7110_PLLCLK_PLL0_OUT>,
899 <&pllclk JH7110_PLLCLK_PLL1_OUT>,
900 <&pllclk JH7110_PLLCLK_PLL2_OUT>;
915 pllclk: clock-controller { label
/linux/include/dt-bindings/clock/
H A Dmicrochip,pic32-clock.h17 #define PLLCLK 6 macro
/linux/drivers/clk/microchip/
H A Dclk-pic32mzda.c208 clks[PLLCLK] = pic32_spll_clk_register(&sys_pll, core); in pic32mzda_clk_probe()