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Searched full:pllb (Results 1 – 15 of 15) sorted by relevance

/linux/arch/arm/boot/dts/vt8500/
H A Dwm8750.dtsi99 pllb: pllb { label
137 clocks = <&pllb>;
144 clocks = <&pllb>;
206 clocks = <&pllb>;
215 clocks = <&pllb>;
225 clocks = <&pllb>;
234 clocks = <&pllb>;
H A Dwm8650.dtsi93 pllb: pllb { label
131 clocks = <&pllb>;
138 clocks = <&pllb>;
168 clocks = <&pllb>;
H A Dwm8850.dtsi96 pllb: pllb { label
148 clocks = <&pllb>;
155 clocks = <&pllb>;
201 clocks = <&pllb>;
210 clocks = <&pllb>;
H A Dwm8505.dtsi96 pllb: pllb { label
127 clocks = <&pllb>;
134 clocks = <&pllb>;
196 clocks = <&pllb>;
/linux/drivers/clk/renesas/
H A Dclk-r8a7778.c50 } else if (!strcmp(name, "pllb")) { in r8a7778_cpg_register_clock()
51 return clk_register_fixed_factor(NULL, "pllb", in r8a7778_cpg_register_clock()
/linux/Documentation/devicetree/bindings/clock/
H A Dvt8500.txt69 clocks = <&pllb>;
/linux/include/linux/clk/
H A Dat91_pmc.h93 #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
97 #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
198 #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
/linux/drivers/video/fbdev/nvidia/
H A Dnv_type.h70 u32 pllB; member
H A Dnv_hw.c874 CalcVClock2Stage(dotClock, &VClk, &state->pll, &state->pllB, in NVCalcStateExt()
/linux/drivers/clk/bcm/
H A Dclk-raspberrypi.c6 * the system clocks we've had to factor out 'pllb' as the firmware 'owns' it.
180 * clock (pllb) which we enable by default as turbo mode will alter multiple
H A Dclk-bcm2835.c538 * loop. Bits 13:14 of ANA1 (PLLA,PLLB,PLLC,PLLD) have been re-purposed in bcm2835_pll_get_prediv_mask()
1734 /* PLLB is used for the ARM's clock. */
1737 .name = "pllb",
1754 .source_pll = "pllb",
/linux/sound/soc/codecs/
H A Drt5682s.c1689 SND_SOC_DAPM_SUPPLY("PLLB", SND_SOC_NOPM, 0, 0,
1851 {"ADC Stereo1 Filter", NULL, "PLLB", is_sys_clk_from_pllb},
1853 {"DAC Stereo1 Filter", NULL, "PLLB", is_sys_clk_from_pllb},
2305 /* Look at PLLB table */ in find_pll_inter_combination()
2313 /* Find a combination of PLLA & PLLB */ in find_pll_inter_combination()
2398 "PLLB: fin=%d fout=%d m_bp=%d k_bp=%d m=%d n=%d k=%d byp_ps=%d sel_ps=%d\n", in rt5682s_set_component_pll()
2551 /* Only need to power on PLLB due to the rate set restriction */ in rt5682s_wclk_prepare()
2584 /* Power down PLLB */ in rt5682s_wclk_unprepare()
/linux/arch/arm/boot/dts/renesas/
H A Dr8a7778.dtsi503 clock-output-names = "plla", "pllb", "b",
/linux/drivers/clk/at91/
H A Ddt-compat.c698 CLK_OF_DECLARE(at91sam9g20_clk_pllb, "atmel,at91sam9g20-clk-pllb",
/linux/drivers/usb/gadget/udc/
H A Dat91_udc.c1961 * PLLB for USB events (signaling for reset, wakeup, or incoming in at91udc_suspend()